Kinematics/Fuzzy Logic Combined Controller for Formation Control of Mobile Robots

A kinematics and fuzzy logic combined formation controller was proposed for leader-follower based formation control using backstepping method in order to accommodate the dynamics of the robot.The kinematics controller generates desired linear and angular velocities for follower robots,which make the configuration of follower robots coverage to the desired.The fuzzy logic controller takes dynamics of the leader and followers into consideration,which is built upon Mamdani fuzzy model.The force and torque acting on robots are described as linguistic variables and also 25 if-then rules are designed.In addition,the fuzzy logic controller adopts the Centroid of Area method as defuzzification strategy and makes robots’actual velocities converge to the expected which is generated by the kinematics controller.The innovation of the kinematics and fuzzy logic combined formation controller presented in the paper is that the perfect velocity tracking assumption is removed and realtime performance of the system is improved.Compared with traditional torque-computed controller,the velocity error convergence time in case of the proposed method is shorter than traditional torque-computed controller.The simulation results validate that the proposed controller can drive robot members to form the desired formation and formation tracking errors which can coverage to a neighborhood of the origin.Additionally,the simulations also show that the proposed method has better velocity convergence performance than traditional torque-computed method.

Enhanced Side-Channel Leakage Detection Method by Considering Combinational Logic

In this paper,we propose a hybrid power model that includes the power consumption of not only the registers but also part of the combinational logic.By doing knownkey analysis with this hybrid model,power side-channel leakage caused by correct keys can be detected.In experiment,PRINTcipher and DES algorithms were chosen as analysis targets and combinational logic s-box unit was selected to build power template.The analysis results showed the signal-to-noise ratio(SNR) power consumption increase of more than 20%after considering s-box's power consumption so that the information of keys can be obtained with just half number of power traces.In addition,the side channel-leakage detection capability of our method also shows better effectiveness that can identify the correct keys.

An Improved GA for Combinational Logic Expressions

This paper discusses complete binary trees as chromosomes of Genetic Algorithm (GA), and proposes the concept of dominant and recessive genes. On the base of it, a new crossover operator with the selective ability was designed. Finally experimental results are presented.

A weighted averaging method for signal probability of logic circuit combined with reconvergent fan-out structures

By analyzing the structures of circuits,a novel approach for signal probability estimation of very large-scale integration(VLSI)based on the improved weighted averaging algorithm(IWAA)is proposed.Considering the failure probability of the gate,first,the first reconvergent fan-ins corresponding to the reconvergent fan-outs were identified to locate the important signal correlation nodes based on the principle of homologous signal convergence.Secondly,the reconvergent fan-in nodes of the multiple reconverging structure in the circuit were identified by the sensitization path to determine the interference sources to the signal probability calculation.Then,the weighted signal probability was calculated by combining the weighted average approach to correct the signal probability.Finally,the reconvergent fan-out was quantified by the mixed-calculation strategy of signal probability to reduce the impact of multiple reconvergent fan-outs on the accuracy.Simulation results on ISCAS85 benchmarks circuits show that the proposed method has approximate linear time-space consumption with the increase in the number of the gate,and its accuracy is 4.2%higher than that of the IWAA.

A Combinational Power Analysis Method against Cryptographic Hardware

Power analysis is a non-invaslve attack against cryptographic hardware, which effectively exploits runtime power consumption characteristics of circuits. This paper proposes a new power model which combines Hamming Distance model and the model based on the template value of power consumption in combinational logic circuit. The new model can describe the power consumption characteristics of sequential logic circuits and those of combinational logic as well. The new model can be used to improve the existing power analysis methods and detect the information leakage of power consumption. Experimental results show that, compared to CPA（Correlation Power Analysis） method, our proposed attack which adopt the combinational model is more efficient in terms of the number of required power traces.

Improved all-optical OR logic gate based on combined Brillouin gain and loss in an optical fiber

Improved all-optical OR gates are proposed, using a novel fiber nonlinearity-based technique, based on the principles of combined Brillouin gain and loss in a polarization-maintaining fiber （PMF）. Switching contrasts are simulated to be between 82.4%-83.6%, for two respective configurations, and switching time is comparable to the phonon relaxation time in stimulated Brillouin scattering （SBS）.

All-atomristor logic gates

The atomristor(monolayer two-dimensional(2D)-material memristor)is competitive in high-speed logic computing due to its binary feature,lower energy consumption,faster switch response,and so on.Yet to date,all-atomristor logic gates used for logic computing have not been reported due to the poor consistency of different atomristors in performance.Here,by studying band structures and electron transport properties of MoS2 atomristor,a comprehensive memristive mechanism is obtained.Guided by the simulation results,monolayer MoS2 with moderated defect concentration has been fabricated in the experiment,which can build atomristors with high performance and good consistency.Based on this,for the first time,MoS2 all-atomristor logic gates are realized successfully.As a demonstration,a half-adder based on the logic gates and a binary neural network(BNN)based on crossbar arrays are evaluated,indicating the applicability in various logic computing circumstances.Owing to shorter transition time and lower energy consumption,all-atomristor logic gates will open many new opportunities for next-generation logic computing and data processing.