Network on chip (NoC) architectures have been proposed to resolve complex on-chip communication problems. An NoC-based mapping algorithm is shown in this paper. It can map irregular intellectual properties (IPs) cores...Network on chip (NoC) architectures have been proposed to resolve complex on-chip communication problems. An NoC-based mapping algorithm is shown in this paper. It can map irregular intellectual properties (IPs) cores onto regular tile 2-D mesh NoC architectures. The basic idea is to decompose a large IP into several dummy IPs or integrate several small IPs into one dummy IP, such that each dummy IP can fit into a single tile. It can also allocate buffer space according to the input/output degree and avoid connection congestion by adapting communication density. Experimental data indicate that using the algorithm proposed in this paper, the communication energy can be reduced about 7%.展开更多
基金the National Natural Science Foundation of China (No. 60273081)
文摘Network on chip (NoC) architectures have been proposed to resolve complex on-chip communication problems. An NoC-based mapping algorithm is shown in this paper. It can map irregular intellectual properties (IPs) cores onto regular tile 2-D mesh NoC architectures. The basic idea is to decompose a large IP into several dummy IPs or integrate several small IPs into one dummy IP, such that each dummy IP can fit into a single tile. It can also allocate buffer space according to the input/output degree and avoid connection congestion by adapting communication density. Experimental data indicate that using the algorithm proposed in this paper, the communication energy can be reduced about 7%.
