A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can b...A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can be effectively reduced by using complementary pass transistor logic and transmission gates.Furthermore,the minimization of the energy consumption can be obtained by choosing the optimal size of bootstrapped nMOS transistors,thus it has more efficient energy transfer and recovery.A three phase power supply generator with a small control logic circuit and a single inductor is proposed.An 8 bit adder based on CPAL is designed and verified.With MOSIS 0 25μm CMOS technology,the CPAL adder consumes only 35% of the dissipated energy of a 2N 2N2P adder and is about 50% of the dissipated energy of a PFAL adder for clock rates ranging from 50 to 200MHz.展开更多
Recently, it has been demonstrated that memristors can be utilized as logic operations and memory elements. In this paper, we present a novel circuit design for complementary resistive switch（CRS）-based stateful log...Recently, it has been demonstrated that memristors can be utilized as logic operations and memory elements. In this paper, we present a novel circuit design for complementary resistive switch（CRS）-based stateful logic operations. The proposed circuit can automatically write the destructive CRS cells back to the original states. In addition, the circuit can be used in massive passive crossbar arrays which can reduce sneak path current greatly. Moreover, the steps for CRS logic operations using our proposed circuit are reduced compared with previous circuit designs. We validate the effectiveness of our scheme through Hspice simulations on the logic circuits.展开更多
Randomness number generation plays a key role in network, information security and IT applications. In this paper, a permutation and complementary algorithm is proposed to use vector complementary and permuta-tion ope...Randomness number generation plays a key role in network, information security and IT applications. In this paper, a permutation and complementary algorithm is proposed to use vector complementary and permuta-tion operations to extend n-variable Logic function space from 22n functions to 22n * 2n! configurations for variant logic framework. Each configuration contains 2n functions can be shown in a 22n-1*22n-1 matrix. A set of visual results can be represented by their symmetric properties in W, F and C codes respec-tively to provide the essential support on the variant logic framework.展开更多
A general method for designing ternary circuits using double pass-transistor logic is investigated. The logical relation of each MOS transistor is formulated by using the transmission operation in order to make effect...A general method for designing ternary circuits using double pass-transistor logic is investigated. The logical relation of each MOS transistor is formulated by using the transmission operation in order to make effective and practical use of the circuits. A way to generate ternary complementary and dual circuits by applying the complementarity and duality principles is presented. This new static ternary double pass-transistor logic scheme has some favorable properties：the use of standard CMOS process without any modification of the thresholds, a perfectly symmetrical structure,a full logic swing, the maximum possible noise margins, a less complex structure, and no static power consumption. HSPICE simulations using TSMC 0.25μm CMOS technology and a 3V power supply demonstrate the effectiveness of the proposed design.展开更多
he logical tree methods are used for evaluate quantitatively relationship between frequency and magnitude, and deduce uncertainties of annual occurrence rate of earthquakes in the periods of lower magnitude earthquake...he logical tree methods are used for evaluate quantitatively relationship between frequency and magnitude, and deduce uncertainties of annual occurrence rate of earthquakes in the periods of lower magnitude earthquake. The uncertainties include deviations from the self-similarity of frequency-magnitude relations, different fitting methods, different methods obtained the annual occurrence rate, magnitude step used in fitting, start magnitude, error of magnitude and so on. Taking Xianshuihe River source zone as an example, we analyze uncertainties of occurrence rate of earthquakes M4, which is needed in risk evaluation extrapolating from frequency-magnitude relations of stronger earthquakes. The annual occurrence rate of M4 is usually required for seismic hazard assessment.The sensitivity analysis and examinations indicate that, in the same frequencymagnitude relations fitting method, the most sensitive factor is annual occurrence rate, the second is magnitude step and the following is start magnitude. Effect of magnitude error is rather small.Procedure of estimating the uncertainties is as follows:①Establishing a logical tree described uncertainties in frequencymagnitude relations by available data and knowledge about studied region.② Calculating frequencymagnitude relations for each end branches. ③ Examining sensitivities of each uncertainty factors, amending structure of logical tree and adjusting original weights. ④ Recalculating frequencymagnitude relations of end branches and complementary cumulative distribution function (CCDF) in each magnitude intervals.⑤ Obtaining an annual occurrence rate of M4 earthquakes under given fractiles.Taking fractiles as 20% and 80%, annual occurrence rate of M 4 events in Xianshuihe seismic zone is 0.643 0. The annual occurrence rate is 0.631 8 under fractiles of 50%, which is very close to that under fractiles 20% and 80%.展开更多
New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study o...New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.展开更多
文摘A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can be effectively reduced by using complementary pass transistor logic and transmission gates.Furthermore,the minimization of the energy consumption can be obtained by choosing the optimal size of bootstrapped nMOS transistors,thus it has more efficient energy transfer and recovery.A three phase power supply generator with a small control logic circuit and a single inductor is proposed.An 8 bit adder based on CPAL is designed and verified.With MOSIS 0 25μm CMOS technology,the CPAL adder consumes only 35% of the dissipated energy of a 2N 2N2P adder and is about 50% of the dissipated energy of a PFAL adder for clock rates ranging from 50 to 200MHz.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61374150 and 11271146)the State Key Program of the National Natural Science Foundation of China(Grant No.61134012)+1 种基金the Doctoral Fund of Ministry of Education of China(Grant No.20130142130012)the Science and Technology Program of Shenzhen City,China(Grant No.JCYJ20140509162710496)
文摘Recently, it has been demonstrated that memristors can be utilized as logic operations and memory elements. In this paper, we present a novel circuit design for complementary resistive switch（CRS）-based stateful logic operations. The proposed circuit can automatically write the destructive CRS cells back to the original states. In addition, the circuit can be used in massive passive crossbar arrays which can reduce sneak path current greatly. Moreover, the steps for CRS logic operations using our proposed circuit are reduced compared with previous circuit designs. We validate the effectiveness of our scheme through Hspice simulations on the logic circuits.
文摘Randomness number generation plays a key role in network, information security and IT applications. In this paper, a permutation and complementary algorithm is proposed to use vector complementary and permuta-tion operations to extend n-variable Logic function space from 22n functions to 22n * 2n! configurations for variant logic framework. Each configuration contains 2n functions can be shown in a 22n-1*22n-1 matrix. A set of visual results can be represented by their symmetric properties in W, F and C codes respec-tively to provide the essential support on the variant logic framework.
文摘A general method for designing ternary circuits using double pass-transistor logic is investigated. The logical relation of each MOS transistor is formulated by using the transmission operation in order to make effective and practical use of the circuits. A way to generate ternary complementary and dual circuits by applying the complementarity and duality principles is presented. This new static ternary double pass-transistor logic scheme has some favorable properties：the use of standard CMOS process without any modification of the thresholds, a perfectly symmetrical structure,a full logic swing, the maximum possible noise margins, a less complex structure, and no static power consumption. HSPICE simulations using TSMC 0.25μm CMOS technology and a 3V power supply demonstrate the effectiveness of the proposed design.
文摘he logical tree methods are used for evaluate quantitatively relationship between frequency and magnitude, and deduce uncertainties of annual occurrence rate of earthquakes in the periods of lower magnitude earthquake. The uncertainties include deviations from the self-similarity of frequency-magnitude relations, different fitting methods, different methods obtained the annual occurrence rate, magnitude step used in fitting, start magnitude, error of magnitude and so on. Taking Xianshuihe River source zone as an example, we analyze uncertainties of occurrence rate of earthquakes M4, which is needed in risk evaluation extrapolating from frequency-magnitude relations of stronger earthquakes. The annual occurrence rate of M4 is usually required for seismic hazard assessment.The sensitivity analysis and examinations indicate that, in the same frequencymagnitude relations fitting method, the most sensitive factor is annual occurrence rate, the second is magnitude step and the following is start magnitude. Effect of magnitude error is rather small.Procedure of estimating the uncertainties is as follows:①Establishing a logical tree described uncertainties in frequencymagnitude relations by available data and knowledge about studied region.② Calculating frequencymagnitude relations for each end branches. ③ Examining sensitivities of each uncertainty factors, amending structure of logical tree and adjusting original weights. ④ Recalculating frequencymagnitude relations of end branches and complementary cumulative distribution function (CCDF) in each magnitude intervals.⑤ Obtaining an annual occurrence rate of M4 earthquakes under given fractiles.Taking fractiles as 20% and 80%, annual occurrence rate of M 4 events in Xianshuihe seismic zone is 0.643 0. The annual occurrence rate is 0.631 8 under fractiles of 50%, which is very close to that under fractiles 20% and 80%.
文摘New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.
