Heavy ion energy influence on multiple-cell upsets in small sensitive volumes:from standard to high energies

The 28 nm process has a high cost-performance ratio and has gradually become the standard for the field of radiation-hardened devices.However,owing to the minimum physical gate length of only 35 nm,the physical area of a standard 6T SRAM unit is approximately 0.16μm^(2),resulting in a significant enhancement of multi-cell charge-sharing effects.Multiple-cell upsets(MCUs)have become the primary physical mechanism behind single-event upsets(SEUs)in advanced nanometer node devices.The range of ionization track effects increases with higher ion energies,and spacecraft in orbit primarily experience SEUs caused by high-energy ions.However,ground accelerator experiments have mainly obtained low-energy ion irradiation data.Therefore,the impact of ion energy on the SEU cross section,charge collection mechanisms,and MCU patterns and quantities in advanced nanometer devices remains unclear.In this study,based on the experimental platform of the Heavy Ion Research Facility in Lanzhou,low-and high-energy heavy-ion beams were used to study the SEUs of 28 nm SRAM devices.The influence of ion energy on the charge collection processes of small-sensitive-volume devices,MCU patterns,and upset cross sections was obtained,and the applicable range of the inverse cosine law was clarified.The findings of this study are an important guide for the accurate evaluation of SEUs in advanced nanometer devices and for the development of radiation-hardening techniques.

Microstructure and mechanical properties of AZ31-Mg_2Si in situ composite fabricated by repetitive upsetting

AZ31-4.6% Mg2Si （mass fraction） composite was prepared by conventional casting method. Repetitive upsetting （RU） was applied to severely deforming the as-cast composite at 400 ℃ for 1, 3, and 5 passes. Finite element analysis of the material flow indicates that deformation concentrates in the bottom region of the sample after 1 pass, and much more uniform deformation is obtained after 5 passes. During multi-pass RU process, both dendritic and Chinese script type Mg2Si phases are broken up into smaller particles owing to the shear stress forced by the matrix. With the increasing number of RU passes, finer grain size and more homogeneous distribution of Mg2Si particles are obtained along with significant enhancement in both strength and ductility. AZ31-4.6%Mg2Si composite exhibits tensile strength of 284 MPa and elongation of 9.8%after 5 RU passes at 400 ℃ compared with the initial 128 MPa and 5.4%of original AZ31-4.6%Mg2Si composite.

Multiple Node Upset in SEU Hardened Storage Cells

We study the problem of multiple node upset （MNU） using three-dimensional device simulation. The results show the transient floating node and charge lateral diffusion are the key reasons for MNU. We compare the MNU with multiple bit upset （MBU）,and find that their characteristics are different. Methods to avoid MNU are also discussed.

Heavy ion-induced single event upset sensitivity evaluation of 3D integrated static random access memory

Heavy ion-induced single event upsets(SEUs)of static random access memory(SRAM), integrated with three-dimensional integrated circuit technology, are evaluated using a Monte Carlo simulation method based on the Geant4 simulation toolkit. The SEU cross sections and multiple cell upset(MCU) susceptibility of 3D SRAM are explored using different types and energies of heavy ions.In the simulations, the sensitivities of different dies of 3D SRAM show noticeable discrepancies for low linear energy transfers(LETs). The average percentage of MCUs of 3D SRAM increases from 17.2 to 32.95%, followed by the energy of ^(209)Bi decreasing from 71.77 to 38.28 MeV/u. For a specific LET, the percentage of MCUs presents a notable difference between the face-to-face and back-toface structures. In the back-to-face structure, the percentage of MCUs increases with a deeper die, compared with the face-to-face structure. The simulation method and process are verified by comparing the SEU cross sections of planar SRAM with experimental data. The upset cross sections of the planar process and 3D integrated SRAM are analyzed. The results demonstrate that the 3D SRAM sensitivity is not greater than that of the planar SRAM. The 3D process technology has the potential to be applied to the aerospace and military fields.

Angular dependence of multiple-bit upset response in static random access memories under heavy ion irradiation

Experimental evidence is presented relevant to the angular dependences of multiple-bit upset （MBU） rates and patterns in static random access memories （SRAMs） under heavy ion irradiation. The single event upset （SEU） cross sections under tilted ion strikes are overestimated by 23.9%-84.6%, compared with under normally incident ion with the equivalent linear energy transfer （LET） value of 41 MeV/（mg/cm2）, which can be partially explained by the fact that the MBU rate for tilted ions of 30° is 8.5%-9.8% higher than for normally incident ions. While at a lower LET of - 9.5 MeV/（mg/cm2）, no clear discrepancy is observed. Moreover, since the ion trajectories at normal and tilted incidences are different, the predominant double-bit upset （DBU） patterns measured are different in both conditions. Those differences depend on the LET values of heavy ions and devices under test. Thus, effective LET method should be used carefully in ground-based testing of single event effects （SEE） sensitivity, especially in MBU-sensitive devices.

Monte Carlo evaluation of spatial multiple-bit upset sensitivity to oblique incidence

We investigate the impact of heavy ion irradiation on a hypothetical static random access memory （SRAM） device. Influences of the irradiation angle, critical charge, drain-drain spacing, and dimension of device structure on the device sensitivity have been studied. These prediction and simulated results are interpreted with MUFPSA, a Monte Carlo code based on Geant4. The results show that the orientation of ion beams and device with different critical charge exert indis- pensable effects on multiple-bit upsets （MBUs）, and that with the decrease in spacing distance between adjacent cells or the dimension of the cells, the device is more susceptible to single event effect, especially to MBUs at oblique incidence.

Physics-based analysis and simulation model of electromagnetic interference induced soft logic upset in CMOS inverter

The instantaneous reversible soft logic upset induced by the electromagnetic interference（EMI） severely affects the performances and reliabilities of complementary metal–oxide–semiconductor（CMOS） inverters. This kind of soft logic upset is investigated in theory and simulation. Physics-based analysis is performed, and the result shows that the upset is caused by the non-equilibrium carrier accumulation in channels, which can ultimately lead to an abnormal turn-on of specific metal–oxide–semiconductor field-effect transistor（MOSFET） in CMOS inverter. Then a soft logic upset simulation model is introduced. Using this model, analysis of upset characteristic reveals an increasing susceptibility under higher injection powers, which accords well with experimental results, and the influences of EMI frequency and device size are studied respectively using the same model. The research indicates that in a range from L waveband to C waveband, lower interference frequency and smaller device size are more likely to be affected by the soft logic upset.

Heavy ion induced upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory

Upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory induced by accelerated ^（129）Xe and ^（209）Bi ions are investigated in detail. The linear energy transfer covers the range from 50 to 99.8 Me V/（mg/cm^2）. When the memory chips are powered off during heavy ions irradiation, single-event-latch-up and single-event-function-interruption are excluded,and only 0-〉1 upset errors in the memory array are observed. These error bit rates seem very difficult to achieve and cannot be simply recovered based on the power cycle. The number of error bits shows a strong dependence on the linear energy transfer（LET）. Under room-temperature annealing conditions, the upset errors can be reduced by about two orders of magnitude using rewrite/reprogram operations, but they subsequently increase once again in a few minutes after the power cycle. High-temperature annealing can diminish almost all error bits, which are affected by the lower LET ^（129）Xe ions. The percolation path between the floating-gate（FG） and the substrate contributes to the radiation-induced leakage current, and has been identified as the root cause of the upset errors of the Flash memory array in this work.

BREAKAGE MECHANISM OF TUNGSTEN BASED ALLOY BLOCK FOR ELECTRO-HEAT UPSETTING

The breakage mechanism of W-Ni-Fe alloy in the process of electro-heat upsetting studied both theoretically and experimetnally, and also the behaviors of crack formation and propagation were analysed. Alloy suffers from corrosion and thermal-mechanical fatigue mutual function. Simultaneously, the practical ways to improve the anvil life was discussed.

Recovery of single event upset in advanced complementary metal-oxide semiconductor static random access memory cells

Using computer-aided design three-dimensional （3D） simulation technology, the recovery mechanism of single event upset and the effects of spacing and hit angle on the recovery are studied. It is found that the multi-node charge collection plays a key role in recovery and shielding the charge sharing by adding guard rings. It cannot exhibit the recovery effect. It is also indicated that the upset linear energy transfer （LET） threshold is kept constant while the recovery LET threshold increases as the spacing increases. Additionally, the effect of incident angle on recovery is analysed and it is shown that a larger angle can bring about a stronger charge sharing effect, thus strengthening the recovery ability.

Unique microstructure and property of a 2024 aluminum alloy subjected to upsetting extrusion multiple processing

The microstructure and hardness of a 2024 aluminum alloy subjected tomulti-pass upsetting extrusion at ambient temperature were studied. Experimental results indicatedthat with the number of upsetting extrusion passes increasing, the grains of the alloy are graduallyrefined and the hardness increases correspondingly. After ten passes of upsetting extrusionprocessing, the grain size decreases to less than 200 nm in diameter and the sample maintains itsoriginal shape, while the hardness is double owing to equal-axial ultrafine grains and workhardening effect caused by large plastic deformation.

The supply voltage scaled dependency of the recovery of single event upset in advanced complementary metal-oxide-semiconductor static random-access memory cells

Using computer-aided design three-dimensional simulation technology,the supply voltage scaled dependency of the recovery of single event upset and charge collection in static random-access memory cells are investigated.It reveals that the recovery linear energy transfer threshold decreases with the supply voltage reducing,which is quite attractive for dynamic voltage scaling and subthreshold circuit radiation-hardened design.Additionally,the effect of supply voltage on charge collection is also investigated.It is concluded that the supply voltage mainly affects the bipolar gain of the parasitical bipolar junction transistor（BJT） and the existence of the source plays an important role in supply voltage variation.

ANALYSIS OF THREE-DIMENSIONAL UPSETTING PROCESS BY THE RIGID-PLASTIC REPRODUCING KERNEL PARTICLE METHOD

A meshless approach, called the rigid-plastic reproducing kernel particle method （RKPM）, is presented for three-dimensional （3D） bulk metal forming simulation. The approach is a combination of RKPM with the flow theory of 3D rigid-plastic mechanics. For the treatments of essential boundary conditions and incompressibility constraint, the boundary singular kernel method and the modified penalty method are utilized, respectively. The arc-tangential friction model is employed to treat the contact conditions. The compression of rectangular blocks, a typical 3D upsetting operation, is analyzed for different friction conditions and the numerical results are compared with those obtained using commercial rigid-plastic FEM （finite element method） software Deform^3D. As results show, when handling 3D plastic deformations, the proposed approach eliminates the need of expensive meshing and remeshing procedures which are unavoidable in conventional FEM and can provide results that are in good agreement with finite element predictions.

Impact of energy straggle on proton-induced single event upset test in a 65-nm SRAM cell

This paper presents a simulation study of the impact of energy straggle on a proton-induced single event upset （SEU） test in a commercial 65-nm static random access memory cell. The simulation results indicate that the SEU cross sections for low energy protons are significantly underestimated due to the use of degraders in the SEU test. In contrast, using degraders in a high energy proton test may cause the overestimation of the SEU cross sections. The results are confirmed by the experimental data and the impact of energy straggle on the SEU cross section needs to be taken into account when conducting a proton-induced SEU test in a nanodevice using degraders.

MECHANICAL ANALYSIS OF CYLINDERS BEING UPSET BETWEEN SPHERICAL CONCAVE PLATEN AND CONCAVE SUPPORTING PLATE

Mechanical analysis of cylinders being upset between spherical concave platen and concave supporting plate is conducted. Rigid-plastic mechanical models for cylinders are presented. When the ratio of height to diameter, is larger than 1, there exists two-dimensional tensile stress in the deformed body, when the ratio is smaller than 1, there exists shear stress in static hydraulic zone. The former breaks through the theory that there is three-dimensional compressive stress irrespective of any ratio of height to diameter. The latter satisfactorily explains the mechanism of layer-like cracks in disk-shaped forgings and the flanges of forged gear axles. The representation of the two models makes the upsetting, theory into correct and perfect stage.

Multiple bit upsets mitigation in memory by using improved hamming codes and parity codes

This paper combines improved Hamming codes and parity codes to assure the reliability of memory in presence of multiple bit upsets with low cost overhead.The redundancy bits of improved Hamming codes will be appended at the end of data bits,which eliminates the overhead of interspersing the redundancy bits at the encoder and decoder.The reliability of memory is further enhanced by the layout architecture of redundancy bits and data bits.The proposed scheme has been implemented in Verilog and synthesized using the Synopsys tools.The results reveal that the proposed method has about 19% less area penalties and 13% less power consumption comparing with the current two-dimensional error codes,and its latency of encoder and decoder is 63% less than that of Hamming codes.

A novel double-node-upset-resilient radiation-hardened latch

To effectively tolerate a double-node upset,a novel double-node-upset-resilient radiation-hardened latch is proposed in 22 nm complementary-metal-oxide-semiconductor technology.Using three interlocked single-node-upset-resilient cells,which are identically mainly constructed from three mutually feeding back 2-input C-elements,the latch achieves double-node-upset-resilience.Using smaller transistor sizes,clock-gating technology,and high-speed transmission-path,the cost of the latch is effectively reduced.Simulation results demonstrate the double-node-upset-resilience of the latch and also show that compared with the up-to-date double-node-upset-resilient latches,the proposed latch reduces the transmission delay by 72.54%,the power dissipation by 33.97%,and the delay-power-area product by 78.57%,while the average cost of the silicon area is only increased by 16.45%.

Azimuthal dependence of single-event and multiple-bit upsets in SRAM devices with anisotropic layout

Experimental evidence is presented showing obvious azimuthal dependence of single event upsets(SEU) and multiple-bit upset(MBU) patterns in radiation hardened by design(RHBD) and MBU-sensitive static random access memories(SRAMs), due to the anisotropic device layouts. Depending on the test devices, a discrepancy from 24.5% to 50% in the SEU cross sections of dual interlock cell(DICE) SRAMs is shown between two perpendicular ion azimuths under the same tilt angle. Significant angular dependence of the SEU data in this kind of design is also observed, which does not fit the inverse-cosine law in the effective LET method. Ion trajectory-oriented MBU patterns are identified, which is also affected by the topological distribution of sensitive volumes. Due to that the sensitive volumes are periodically isolated by the BL/BLB contacts along the Y-axis direction, double-bit upsets along the X-axis become the predominant configuration under normal incidence.Predominant triple-bit upset and quadruple-bit upset patterns are the same under different ion azimuths(Lshaped and square-shaped configurations, respectively). Those results suggest that traditional RPP/IRPP model should be promoted to consider the azimuthal and angular dependence of single event effects in certain designs.During earth-based evaluation of SEE sensitivity, worst case beam direction, i.e., the worst case response, should be revealed to avoid underestimation of the on-orbit error rate.

Velocity Field and Variation of Wall Thickness During Tube Dieless Upsetting

Theoretical analyses show that the variation of wall thickness is in direct proportion to outer-diameter, inter-diameter, and (1+R_s)^(1/2) (Rs is sectional increase ratio of tube), the theoretical calculated results of wall thickness during tube dieless upsetting are very approximate to the experimental one. As the width of deformation field increases, both the variation of wall thickness and the derivative of wall thickness variation to width of deformation field (to/tf) reduce.

Heavy ion‑induced MCUs in 28nm SRAM‑based FPGAs:upset proportions,classifications,and pattern shapes

For modern scaling devices,multiple cell upsets(MCUs)have become a major threat to high-reliability field-programmable gate array(FPGA)-based systems.Thus,both performing the worst-case irradiation tests to provide the actual MCU response of devices and proposing an effective MCU distinction method are urgently needed.In this study,high-and medium-energy heavy-ion irradiations for the configuration random-access memory of 28 nm FPGAs are performed.An MCU extraction method supported by theoretical predictions is proposed to study the MCU sizes,shapes,and frequencies in detail.Based on the extraction method,the different percentages,and orientations of the large MCUs in both the azimuth and zenith directions determine the worse irradiation response of the FPGAs.The extracted largest 9-bit MCUs indicate that high-energy heavy ions can induce more severe failures than medium-energy ones.The results show that both the use of high-energy heavy ions during MCU evaluations and effective protection for the application of high-density 28 nm FPGAs in space are extremely necessary.