Design and implementation of instruction-driven and data-driven self-reconfigurable cell array

The reconfigurable chip,which integrates the advantages of high performance,high flexibility,high parallelism,low power consumption,and low cost,has achieved rapid development and wide application.Generally,the control part and the computing part of algorithm is accelerated based on different reconfigurable architectures,but it is difficult to obtain overall performance improvement.For improving efficiency of reconfigurable structure both for the control part and the computing part,a hybrid of instruction-driven and data-driven self-reconfigurable cell array is proposed.On instruction-driven mode,processing element(PE)works like a reduced instruction set computer(RSIC)machine,which is mainly for the control part of algorithm.On data-driven mode,data is calculated by flowing between the preconfigured PEs,which is mainly for the computing of algorithm.For verifying the efficiency of architecture,some high-efficiency video coding(HEVC)video compression algorithms are implemented on the proposed architecture.The proposed architecture has been implemented on Xilinx FPGA Virtex UltraScale VU440 develop board.The same circuitry is able to run at75 MHz.Compared with the architecture that only supports instruction-driven,the proposed architecture has better calculation efficiency.

Dynamical Self-Reconfigurable Mechanism for Data-Driven Cell Array

The utilization of computation resources and reconfiguration time has a large impact on reconfiguration system performance. In order to promote the performance, a dynamical self-reconfigurable mechanism for data-driven cell array is proposed. Cells can be fired only when the needed data arrives, and cell array can be worked on two modes: fixed execution and reconfiguration. On reconfiguration mode, cell function and data flow direction are changed automatically at run time according to contexts. Simultaneously using an H-tree interconnection network, through pre-storing multiple application mapping contexts in reconfiguration buffer, multiple applications can execute concurrently and context switching time is the minimal. For verifying system performance, some algorithms are selected for mapping onto the proposed structure, and the amount of configuration contexts and execution time are recorded for statistical analysis. The results show that the proposed self-reconfigurable mechanism can reduce the number of contexts efficiently, and has a low computing time.

Aerodynamic Design Methodology for Blended Wing Body Transport

This paper puts forward a design idea for blended wing body（BWB）.The idea is described as that cruise point,maximum lift to drag point and pitch trim point are in the same flight attitude.According to this design idea,design objectives and constraints are defined.By applying low and high fidelity aerodynamic analysis tools,BWB aerodynamic design methodology is established by the combination of optimization design and inverse design methods.High lift to drag ratio,pitch trim and acceptable buffet margin can be achieved by this design methodology.For 300-passenger BWB configuration based on static stability design,as compared with initial configuration,the maximum lift to drag ratio and pitch trim are achieved at cruise condition,zero lift pitching moment is positive,and buffet characteristics is well.Fuel burn of 300-passenger BWB configuration is also significantly reduced as compared with conventional civil transports.Because aerodynamic design is carried out under the constraints of BWB design requirements,the design configuration fulfills the demands for interior layout and provides a solid foundation for continuous work.