The paper deals with analysis and synthesis of non-harmonic and non-linear sources and appliances, and their interaction with harmonic power supply network. Basic idea is based on knowledge of harmonic spectrum of the...The paper deals with analysis and synthesis of non-harmonic and non-linear sources and appliances, and their interaction with harmonic power supply network. Basic idea is based on knowledge of harmonic spectrum of the sources and/or appliances, respectively. Obviously, one need to know voltage harmonic components of voltage sources （renewable with inverters,...）, and current harmonic components generated by non-linear appliances （rectifiers,...）. Method of investigation lies on decomposition of real electric circuit into n-harmonic separated equivalent schemes for each harmonic component. Then transient analysis will be done for each scheme separately using ＂impedance harmonic matrices＂. The important fact is that each equivalent scheme is now linearized and therefore easily calculated. Finally, the effects of each investigated schemes arc summed into resulting quantities of real non-linear electric circuit.展开更多
A 2.5 GS/s 14-bit D/A converter（DAC） with 8 to 1 MUX is presented. This 14-bit DAC uses a ＂5＋9＂segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger out...A 2.5 GS/s 14-bit D/A converter（DAC） with 8 to 1 MUX is presented. This 14-bit DAC uses a ＂5＋9＂segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger output impedance under every PVT（process, source voltage and temperature） corner is also presented. The8 to 1 MUX has a 3 stage structure, and a proper timing sequence is designed to ensure reliable data synthesis. A DEM function which is merged with a ＂5-31＂decoder is used to improve the DAC＇s dynamic performance. This DAC is embedded in a 2.5 GHz direct digital frequency synthesizer（DDS） chip, and is implemented in a 0.18 m CMOS technology, occupies 4.86 2. 28 mm-2 including bond pads（DAC only）, and the measured performance is SFDR 〉 40 d B（with and without DEM） for output signal frequency up to 1 GHz. Compared with other present published DACs with a non-analog-resample structure（means return-to-zero or quad-switch structure is unutilized）,this paper DAC＇s clock frequency（2.5 GHz） and higher output frequency SFDR（〉 40 d B, up to 1 GHz） has some competition.展开更多
文摘The paper deals with analysis and synthesis of non-harmonic and non-linear sources and appliances, and their interaction with harmonic power supply network. Basic idea is based on knowledge of harmonic spectrum of the sources and/or appliances, respectively. Obviously, one need to know voltage harmonic components of voltage sources （renewable with inverters,...）, and current harmonic components generated by non-linear appliances （rectifiers,...）. Method of investigation lies on decomposition of real electric circuit into n-harmonic separated equivalent schemes for each harmonic component. Then transient analysis will be done for each scheme separately using ＂impedance harmonic matrices＂. The important fact is that each equivalent scheme is now linearized and therefore easily calculated. Finally, the effects of each investigated schemes arc summed into resulting quantities of real non-linear electric circuit.
基金Project supported by the National Natural Science Foundation of China(Nos.61006027,61176030)the Research Foundation of Key Laboratory of Analog Integrated Circuit(Nos.9140C0902120C09034,9140c090204130c09042)the Fundamental Research Funds for the Central Universities of China(No.ZYGX2012J003)
文摘A 2.5 GS/s 14-bit D/A converter（DAC） with 8 to 1 MUX is presented. This 14-bit DAC uses a ＂5＋9＂segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger output impedance under every PVT（process, source voltage and temperature） corner is also presented. The8 to 1 MUX has a 3 stage structure, and a proper timing sequence is designed to ensure reliable data synthesis. A DEM function which is merged with a ＂5-31＂decoder is used to improve the DAC＇s dynamic performance. This DAC is embedded in a 2.5 GHz direct digital frequency synthesizer（DDS） chip, and is implemented in a 0.18 m CMOS technology, occupies 4.86 2. 28 mm-2 including bond pads（DAC only）, and the measured performance is SFDR 〉 40 d B（with and without DEM） for output signal frequency up to 1 GHz. Compared with other present published DACs with a non-analog-resample structure（means return-to-zero or quad-switch structure is unutilized）,this paper DAC＇s clock frequency（2.5 GHz） and higher output frequency SFDR（〉 40 d B, up to 1 GHz） has some competition.
