A 5MS/s 12-Bit Successive Approximation Analog-to-Digital Converter

With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.

Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters: State-of-the-Art and a Design Example

This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.

Effect of ionizing radiation on dual 8-bit analog-to-digital converters (AD9058) with various dose rates and bias conditions

The radiation effects on several properties （reference voltage, digital output logic voltage, and supply current） of dual 8-bit analog-to-digital （A/D） converters （AD9058） under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity （ELDRS） under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.

Design of Digital to Analog Converters with Arbitrary Radix

There are DAC structures available in the literature for radix r = 2, 3, and 4;but how they are arrived at is missing. No general structure is available for any radix r. The aim of the paper is, therefore, to fulfil these gaps. To start with, the design relations are derived for the simplest possible attenuator circuit when connected to a voltage source V and a series resistance R, such that the complete circuit offers the Thevenin resistance R. Spread relations for this attenuator are derived. An example when 3 such attenuators with different attenuation constants are connected in cascade is given. Interestingly, the two attenuators with attenuation factors 1/2 and 1/3 have the same spread of 2. A generalized attenuator is then obtained when N number of identical attenuators are connected in cascade. This is modified to derive a digital to analog converter for any radix r.

A 1.5 bit/s Pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch

A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.

Novel Optical Analog-To-Digital Converter Based on Optical Time Division Multiplexing

A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.

Analog-to-digital conversion of information in the retina

We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.

A FAST FOREGROUND DIGITAL CALIBRATION TECHNIQUE FOR PIPELINED ADC

Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the analysis of error sources which influence the resolution of pipelined ADCs. This method estimates the gain error of the ADC prototype quickly and calibrates the ADC simultaneously in the operation time. Finally, a 10 bit, 100 Ms/s pipelined ADC is implemented and calibrated. The simulation results show that the digital calibration technique has its efficiency with fewer operation cycles.

320×240 Pixels CMOS Digital Image Sensor with Wide Dynamic Range

A 320×240 CMOS image sensor is demonstrated,which is implemented by a standard 0.6 μm 2P2M CMOS process.For reducing the chip area,each 2×2-pixel block shares a sample/hold circuit,analog-to-digital converter and 1-b memory.The 2×2 pixel pitch has an area of 40 μm×40 μm and the fill factor is about 16%.While operating at a low frame rate,the sensor dissipates a very low power by power-management circuit making pixel-level comparators in an idle state.A digital correlated double sampling,which eliminates fixed pattern noise,improves SNR of the sensor, and multiple sampling operations make the sensor have a wide dynamic range.

DIGITAL BACKGROUND CALIBRATION OF CAPACITOR MISMATCHES AND HARMONIC DISTORTION IN PIPELINED ADC

A correlation-based digital background calibration algorithm for pipelined Analog-to- Digital Converters (ADCs) is presented in this paper. The merit of the calibration algorithm is that the main errors information, which include the capacitor mismatches and residue amplifier distortion, are extracted integrally. A modified 1st pipelined stage is adopted to solve the signal overflow caused by the Pseudo-random Noise (PN) sequences. Behavioral simulation results verify the effectiveness of the algorithm. It improves the Signal-to-Noise-plus-Distortion Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) of the pipelined ADC from 41.8 dB to 78.3 dB and 55.6 dB to 98.6 dB, respectively, which is comparable to the prior arts.

一种应用于12 bit SAR ADC C-R混和式DAC

针对ADC中功耗、精度与成本之间相互制约的问题,提出一种应用于12 bitSARADC的混合电容电阻型(C-R)DAC结构。高6位采用温度计编码的电容阵列结构;低6位选择电阻阵列结构。对电路进行非线性分析选取合理的元件尺寸。另外,采用非交叠时钟电路作为开关控制时序,避免开关切换时引起瞬态毛刺导致电容电荷泄露。基于GSMC 95 nm工艺,完成电路、版图设计与仿真,并完成流片测试,DAC版图总面积为317.2μm×262.5μm,流片测试结果表明,DNL的范围为-0.38~+0.44 LSB,INL的范围为-0.73~+0.4 LSB,满足12位ADC的设计要求。

基于量子电压的模数转换器性能评估

相比于用传统半导体器件研制的信号源,约瑟夫森任意波形发生器合成信号的幅值可溯源至自然常数,其输出波形具有超低噪声、超低失真的优点。使用约瑟夫森任意波形发生器评估了National Instruments公司24位数字采集卡PXI 5922的性能。其中,采用零补偿波形合成方法简化系统硬件结构,并且使用高精度、多比例的感应分压器提升评估效率。首先,在10 kHz的带宽内标定了PXI 5922单通道的增益及其稳定性、信噪比、无杂散动态范围、总谐波失真、信纳比和有效位数;其次,标定了PXI 5922两通道不同相位下的相位差;最后,结合电网的谐波情况,以60 Hz的基波频率为例,标定了PXI 5922在12阶谐波以内各谐波的幅度与相位响应。约瑟夫森任意波形发生器的超高精度和宽带输出能力在评估高精度模数转换器的性能方面具有广阔的应用前景。

一种16位110 dB无杂散动态范围的低功耗SAR ADC

该文设计了一款16位、转换速率为625 kS/s的逐次逼近寄存器型模数转换器(SAR ADC)。改进的采样保持电路结构,优化了采样线性度和噪声性能。采用分段结构设计电容型数模转换器并使用混合方式的电容切换方案,减小面积和能耗。利用扰动注入技术提升ADC的线性度。比较器采用两级积分型预放大器减小噪声,利用输出失调存储技术及优化的电路设计减小了比较器失调电压和失调校准引入的噪声,优化并提升了比较器速度。芯片采用CMOS 0.18μm工艺设计和流片,ADC核心面积为1.15 mm^(2)。测试结果表明,在1 kHz正弦信号输入下,ADC差分输入峰峰值幅度达8.8 V,信纳比为85.9 dB,无杂散动态范围为110 dB,微分非线性为-0.27/+0.32 LSB,积分非线性为-0.58/+0.53 LSB,功耗为4.31 mW。

基于高速ADC的数字双混频时差测量系统

使用双混频时差法进行时间和频率测量时,模拟部分引入的噪声会干扰信号过零点的判断,降低测量精度,而使用数字信号处理技术后不再需要判断过零点,量化噪声成为系统内的主要噪声来源,可以通过数字滤波器对其进行抑制。同时有利于设计结构紧凑的系统,更易于小型化,测量速度也可以进行灵活配置。通过引入高速模数转换器、数控振荡器、低通抽取滤波器、数字鉴相器等,设计了数字双混频时差测量系统,并研制了4通道的原理样机。测试结果表明,当频率源为10 MHz的信号时,原理样机中属于同片ADC(analog-to-digital converter)的两个通道间的本底噪声约为5×10^(-14)@1 s,属于不同片ADC的两个通道间的本底噪声约为8×10^(-14)@1 s,满足原子振荡器的测量要求。并以主动型氢钟VCH-1003M为参考,使用原理样机分别对Microchip的5071A铯原子钟和SRS的FS725铷原子钟的稳定度进行测量,测量结果与Microchip的相噪分析仪53100A和5120A无显著差异。

基于DAC阵列的光交叉芯片控制驱动系统

为标定光交叉芯片驱动电压,控制光交叉芯片实现光路由功能,提出并搭建了基于多通道DAC(Digital to Analog Converter)阵列的控制驱动电路系统。系统主要由控制系统模块、多路驱动电路模块及上位机控制模块构成。控制电路和驱动电路具有调校简单、可双极性输出、输出路数多、加电精确度较高的特点,解决了当前驱动电路工作繁琐、加电极性单一、加电路数少、精度差的问题。上位机控制模块除了可控制驱动电路施加控制电压外,还可接收来自数据采集装置采集到的光功率信号作为控制驱动系统的反馈信号。通过分析控制电压与光功率之间的关系,可得到最佳的光交叉芯片控制驱动电压。系统测试实验结果表明,该系统能提供高精确度的双极性驱动电压,有效地对光交叉芯片进行驱动。可在较短的时间内标定出光开关的控制电压,完全可以满足有源光交叉芯片控制中对驱动电压的需求。该系统在光交叉芯片控制方面具有一定的应用价值。

差动式电容传感器信号检测方法研究

为了提高差动式电容传感器信号检测电路的测量精度,本文提出了一种将增量总和调制技术和差动式电容传感器相结合,做成一个新型信号检测系统的方法。该信号检测方法将差动式电容传感器、前置放大器和相敏检波电路放置在增量总和反馈环路内,形成一个大的反馈环路。本文通过推导该检测电路的系统传递函数,分析该检测方法中利用增量总和调制技术的技术优点,根据该方法设计一版电路板并进行试验。研究结果表明,本文提出的信号检测方法的输出数字量与中心极板偏离平衡位置的大小和方向具有很高的相关性,对进一步提高差动式电容传感器检测电路的测量精度具有较好的促进作用。

基于ARM和FPGA的数字多道分析器研制

多道分析器作为γ能谱测量中不可或缺的组件,其性能直接影响能谱仪分辨率及测量精度,传统的多道分析器多采用模拟电路方法或使用数字采集卡实现。模拟多道对于影响能谱仪性能的成形时间、脉冲通过率及死区时间修正等问题上具有一定的局限性,而这会直接影响能谱分析结果;数字采集卡是实现数字采集的计算机扩展卡,成本较高,不利于市场化推广。数字多道分析器对脉冲信号进行全数字采样,将其转化为数字量,利用数字信号处理方法,通过软件实现,完成整个信号分析处理过程,可极大提高系统稳定性与可靠性,相比于前两种方案,优势明显。设计了一款数字多道分析器,采用ARM处理器+高速ADC+FPGA的硬件方案,主要包括AD采样模块、FPGA数据处理模块和以STM32F4为核心的控制和通信模块。使用数字信号处理方法,编写硬件描述代码实现了脉冲信号滤波成型、幅值提取和基线修正等核脉冲处理的关键算法,最后给出探测器核信号经本文设计的数字多道处理后的γ能谱图。根据国内外研究成果及理论基础,经过深入系统理论分析,方法仿真验证,以及实际调试过程,最终研制出一款可商业化实用、完整且高精度的数字多道分析器,并将其应用在低本底γ能谱仪上,其能量分辨率测试均值为6.6791%,能量线性相关度R2在0.9999以上,积分非线性为0.26%。设计的数字化多道分析器采用ARM+FPGA的方式,极大程度降低了系统设计难度和成本,实现了高精度、高速的脉冲信号数字化,测试性能可达到数字采集卡的水平,具有极高的市场应用价值。

高精度低功耗噪声整形SAR ADC设计

针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损积分优点的同时具有良好噪声整形效果。设计了一款分辨率为16 bit、采样率为2 Ms/s的混合架构噪声整形SAR ADC。仿真结果表明,在125 kHz带宽、过采样比为8时,实现了高信号与噪声失真比(SNDR(Signal to Noise and Distortion Ratio)为91.1 dB)、高精度(14.84 bit)和低功耗(285μW)的性能。

一种具有1~128倍可变增益放大器的低功耗Sigma⁃Delta ADC

为满足传感器应用的低功耗需求,设计并实现了一种低功耗Sigma⁃Delta模数转换器(ADC)芯片。该ADC采用一阶全差分开关电容Sigma⁃Delta调制器,且集成了可编程增益放大器(PGA)和Bandgap;使用1.5 bit量化结构,相较于1 bit量化结构减小了3 dB的量化误差;使用优化的反馈电路,减小了电容失配引入的误差;PGA采用轨到轨的运放电路拓扑,增大了整个芯片的电压适应范围。基于180 nm CMOS工艺对该ADC进行了设计和流片。测试结果表明:该Sigma⁃Delta ADC在采样频率512 kHz、过采样率(OSR)为256时,峰值信噪谐波失真比(SNDR)和有效位数(ENOB)分别为75.29 dB和12.21 bit,芯片功耗仅为0.92 mW。芯片能在2.3~5.5 V宽电源电压范围内正常工作,可实现最大128 V/V的增益。适用于小型传感器的信号测量应用,可以满足小型传感器低功耗、高精度的需求。

一种12位低功耗电阻串架构DAC

利用分段式电阻串结构,基于CMOS工艺设计了一款12位3.4 MHz低功耗数模转换器(DAC)芯片。结合建立速度和静态性能的设计指标,确定“5+7”式分段结构,在保证建立速度的条件下考虑到电阻的失配性,实现良好的微分非线性(DNL)和积分非线性(INL)特性。后仿真结果表明,在3.4 MHz速度下,常温下DNL为0.14 LSB,INL为1 LSB,在-40~125℃下,DNL为0.6 LSB,INL为2 LSB,并且表现出-84 dB的总谐波失真(THD),以及在3 V电压下378μW的极低功耗,版图面积缩小到1.09 mm×0.91 mm。