To overcome the drawbacks such as irregular circuit construction and low system throughput that exist in conventional methods, a new factor correction scheme for coordinate rotation digital computer（ CORDIC） algorit...To overcome the drawbacks such as irregular circuit construction and low system throughput that exist in conventional methods, a new factor correction scheme for coordinate rotation digital computer（ CORDIC） algorithm is proposed. Based on the relationship between the iteration formulae, a new iteration formula is introduced, which leads the correction operation to be several simple shifting and adding operations. As one key part, the effects caused by rounding error are analyzed mathematically and it is concluded that the effects can be degraded by an appropriate selection of coefficients in the iteration formula. The model is then set up in Matlab and coded in Verilog HDL language. The proposed algorithm is also synthesized and verified in field-programmable gate array （FPGA）. The results show that this new scheme requires only one additional clock cycle and there is no change in the elementary iteration for the same precision compared with the conventional algorithm. In addition, the circuit realization is regular and the change in system throughput is very minimal.展开更多
The implementation of the coordinate rotational digital computer （CORDIC） algorithm with wave pipelining technique on field programmable gate array （FPGA） is described. All data in FPGA-based wave pipelining pass ...The implementation of the coordinate rotational digital computer （CORDIC） algorithm with wave pipelining technique on field programmable gate array （FPGA） is described. All data in FPGA-based wave pipelining pass through a number of logic gates, in the same way that all data pass through the same number of registers in a conventional pipeline. Moreover, all paths are routed using identical routing resources. The manual placement, timing driven routing and timing analyzing techniques are applied to optimize the layout for achieving good path balance. Experimental results show that a 256-LUT logic depth circuit mapped on XC4VLX15-12 runs as high as 330 MHz, whichis a little lower than the speed of 336 MHz based on the conventional 16-stage pipelining in the same chip. The latency of the wave pipelining circuit is 30.3 ns, which is 36.4% shorter than the latency of 16-stage conventional pipelining circuit.展开更多
It is an important problem that we implement floating point trigonometric functions of high precision with suitable hardware cost for high performance in digit image processing. The coordinate rotational digital compu...It is an important problem that we implement floating point trigonometric functions of high precision with suitable hardware cost for high performance in digit image processing. The coordinate rotational digital computer （CORDIC） arithmetic to is used to solve the above problem in this paper. In order to increase the speed of operation, it chooses the pipeline architecture. The results are disposed by IEEE-754 standard. The CORDIC architecture is modeled by using the verilog HDL and verified with MATLAB program and ModelSim 6.2SE tool. A 32 bits radix-2 CORDIC architecture was implemented on the available FPGA platform. The entire CORDIC architecture operated at 126.34 MHz of clock rate with a power consumption of 318.56 mW. Its theoretical background, procedures, simulation results and conclusions are presented in this paper.展开更多
本文提出了一种基于CORDIC (Coordinate Rotation Digital Computer)算法的数字鉴频方法。首先给出了基于CORDIC算法的鉴相原理,讨论了CORDIC算法的鉴相范围;然后讨论了差分鉴频的方法,特别是对低数据率情况下的差分鉴频进行了探讨,并...本文提出了一种基于CORDIC (Coordinate Rotation Digital Computer)算法的数字鉴频方法。首先给出了基于CORDIC算法的鉴相原理,讨论了CORDIC算法的鉴相范围;然后讨论了差分鉴频的方法,特别是对低数据率情况下的差分鉴频进行了探讨,并给出了一种实用的数字鉴频结构。计算机仿真结果和FPGA仿真结果表明,基于CORDIC算法流水结构和一阶差分结构实现的数字鉴频方法是可行的,而且是高效的。展开更多
针对传统串行坐标旋转数字计算方法(CORDIC)耗时且占用较多资源的缺点,提出了一种旋转模式下CORDIC算法的新型改进算法,该改进算法可用来代替直接数字频率合成器(DDS)查找表进行正余弦的计算。通过采用贪婪算法实现对CORDIC旋转方向与...针对传统串行坐标旋转数字计算方法(CORDIC)耗时且占用较多资源的缺点,提出了一种旋转模式下CORDIC算法的新型改进算法,该改进算法可用来代替直接数字频率合成器(DDS)查找表进行正余弦的计算。通过采用贪婪算法实现对CORDIC旋转方向与旋转角度的优化,从而可以达到串行转并行和减少迭代次数、节约资源的目的。该算法可以应用于三角函数的复杂函数的硬件实现中。仿真结果表明,在迭代次数相同的情况下,改进算法较传统算法可以获得更高的精度。最后,在Xilinx FPGA的Spartan-3E芯片上实现了改进的CORDIC结构。与传统CORDIC算法相比,在运算精度为10-5时,可以节省Slices、LUTs(Look Up Tables)资源分别为28%和25%。展开更多
为了对流水线结构的坐标旋转数字计算(Coordinate Rotation Digital Computer,CORDIC)的实现时延和硬件资源消耗进行优化,提出一种仅基于查找表的新的实现方法,完全免除了迭代运算.该方法只需要一个较低容量的ROM表,以及对ROM表输出结...为了对流水线结构的坐标旋转数字计算(Coordinate Rotation Digital Computer,CORDIC)的实现时延和硬件资源消耗进行优化,提出一种仅基于查找表的新的实现方法,完全免除了迭代运算.该方法只需要一个较低容量的ROM表,以及对ROM表输出结果进行简单的移位运算,即可得到高精度的正弦波或余弦波输出.分别在Matlab、Modelsim以及XILINX ISE进行了理论仿真及实际验证,结果表明:这种CORDIC实现方法只需要2个时钟周期的处理延时,硬件资源消耗与其他实现方法相比也有所降低,最大工作频率也有一定提高.展开更多
固定角度旋转的CORDIC(Coordinate Rotation Digital Computer)算法已经广泛的应用于高速数字信号处理、图像处理、机器人学等领域.针对固定角度旋转CORDIC算法在相位旋转过程中,存在数据吞吐率较高、占用硬件资源较多且资源消耗量大等...固定角度旋转的CORDIC(Coordinate Rotation Digital Computer)算法已经广泛的应用于高速数字信号处理、图像处理、机器人学等领域.针对固定角度旋转CORDIC算法在相位旋转过程中,存在数据吞吐率较高、占用硬件资源较多且资源消耗量大等缺点,提出了利用混合CORDIC算法,将角度旋转分为单向角度旋转和一次角度估计旋转两部分.本文根据欠阻尼理论,将固定角度旋转采用单向旋转CORDIC算法实现,减少了流水线的级数和迭代符号位的判决,然后通过对角度估计旋转的二进制表示,修正常数因子,再根据角度映射关系进行相关处理,完成高速高精度坐标旋转.最后在硬件平台上进行了仿真实验.实验结果表明,在误差范围一定的前提下,混合算法进一步的减少了迭代次数,并且资源消耗较低,提高了数据吞吐率.展开更多
基金The National High Technology Research and Development Program of China (863 Program)(No.2007AA01Z280)
文摘To overcome the drawbacks such as irregular circuit construction and low system throughput that exist in conventional methods, a new factor correction scheme for coordinate rotation digital computer（ CORDIC） algorithm is proposed. Based on the relationship between the iteration formulae, a new iteration formula is introduced, which leads the correction operation to be several simple shifting and adding operations. As one key part, the effects caused by rounding error are analyzed mathematically and it is concluded that the effects can be degraded by an appropriate selection of coefficients in the iteration formula. The model is then set up in Matlab and coded in Verilog HDL language. The proposed algorithm is also synthesized and verified in field-programmable gate array （FPGA）. The results show that this new scheme requires only one additional clock cycle and there is no change in the elementary iteration for the same precision compared with the conventional algorithm. In addition, the circuit realization is regular and the change in system throughput is very minimal.
文摘The implementation of the coordinate rotational digital computer （CORDIC） algorithm with wave pipelining technique on field programmable gate array （FPGA） is described. All data in FPGA-based wave pipelining pass through a number of logic gates, in the same way that all data pass through the same number of registers in a conventional pipeline. Moreover, all paths are routed using identical routing resources. The manual placement, timing driven routing and timing analyzing techniques are applied to optimize the layout for achieving good path balance. Experimental results show that a 256-LUT logic depth circuit mapped on XC4VLX15-12 runs as high as 330 MHz, whichis a little lower than the speed of 336 MHz based on the conventional 16-stage pipelining in the same chip. The latency of the wave pipelining circuit is 30.3 ns, which is 36.4% shorter than the latency of 16-stage conventional pipelining circuit.
基金supported by the Shanghai AM Foundation(Grant No.09700714000)
文摘It is an important problem that we implement floating point trigonometric functions of high precision with suitable hardware cost for high performance in digit image processing. The coordinate rotational digital computer （CORDIC） arithmetic to is used to solve the above problem in this paper. In order to increase the speed of operation, it chooses the pipeline architecture. The results are disposed by IEEE-754 standard. The CORDIC architecture is modeled by using the verilog HDL and verified with MATLAB program and ModelSim 6.2SE tool. A 32 bits radix-2 CORDIC architecture was implemented on the available FPGA platform. The entire CORDIC architecture operated at 126.34 MHz of clock rate with a power consumption of 318.56 mW. Its theoretical background, procedures, simulation results and conclusions are presented in this paper.
文摘本文提出了一种基于CORDIC (Coordinate Rotation Digital Computer)算法的数字鉴频方法。首先给出了基于CORDIC算法的鉴相原理,讨论了CORDIC算法的鉴相范围;然后讨论了差分鉴频的方法,特别是对低数据率情况下的差分鉴频进行了探讨,并给出了一种实用的数字鉴频结构。计算机仿真结果和FPGA仿真结果表明,基于CORDIC算法流水结构和一阶差分结构实现的数字鉴频方法是可行的,而且是高效的。
文摘针对传统串行坐标旋转数字计算方法(CORDIC)耗时且占用较多资源的缺点,提出了一种旋转模式下CORDIC算法的新型改进算法,该改进算法可用来代替直接数字频率合成器(DDS)查找表进行正余弦的计算。通过采用贪婪算法实现对CORDIC旋转方向与旋转角度的优化,从而可以达到串行转并行和减少迭代次数、节约资源的目的。该算法可以应用于三角函数的复杂函数的硬件实现中。仿真结果表明,在迭代次数相同的情况下,改进算法较传统算法可以获得更高的精度。最后,在Xilinx FPGA的Spartan-3E芯片上实现了改进的CORDIC结构。与传统CORDIC算法相比,在运算精度为10-5时,可以节省Slices、LUTs(Look Up Tables)资源分别为28%和25%。
文摘为了对流水线结构的坐标旋转数字计算(Coordinate Rotation Digital Computer,CORDIC)的实现时延和硬件资源消耗进行优化,提出一种仅基于查找表的新的实现方法,完全免除了迭代运算.该方法只需要一个较低容量的ROM表,以及对ROM表输出结果进行简单的移位运算,即可得到高精度的正弦波或余弦波输出.分别在Matlab、Modelsim以及XILINX ISE进行了理论仿真及实际验证,结果表明:这种CORDIC实现方法只需要2个时钟周期的处理延时,硬件资源消耗与其他实现方法相比也有所降低,最大工作频率也有一定提高.
文摘固定角度旋转的CORDIC(Coordinate Rotation Digital Computer)算法已经广泛的应用于高速数字信号处理、图像处理、机器人学等领域.针对固定角度旋转CORDIC算法在相位旋转过程中,存在数据吞吐率较高、占用硬件资源较多且资源消耗量大等缺点,提出了利用混合CORDIC算法,将角度旋转分为单向角度旋转和一次角度估计旋转两部分.本文根据欠阻尼理论,将固定角度旋转采用单向旋转CORDIC算法实现,减少了流水线的级数和迭代符号位的判决,然后通过对角度估计旋转的二进制表示,修正常数因子,再根据角度映射关系进行相关处理,完成高速高精度坐标旋转.最后在硬件平台上进行了仿真实验.实验结果表明,在误差范围一定的前提下,混合算法进一步的减少了迭代次数,并且资源消耗较低,提高了数据吞吐率.
