An IEEE 1149.x Embedded Test Coprocessor

This paper describes a microprogrammed architecture for an embedded coprocessor that is able to control IEEE 1149.1 to IEEE 1149.7 test infrastructures, and explains how to expand the supported test command set. The coprocessor uses a fast simplex link (FSL) channel to interface a 32-bit MicroBlaze CPU, but it can work with any microprocessor core that accepts this simple FIFO-based interface method. The implementation cost (logic resource usage for a Xilinx Spartan-6 FPGA) and the performance data (operating frequency) are presented for a test command set comprising two parts: 1) the full IEEE 1149.1 structural test operations;2) a subset of IEEE 1149.7 operations selected to illustrate the implementation of advanced scan formats.

基于云存储视频处理框架的研究与实现

随着智慧城市的快速发展,视频技术作为基础数据采集手段已经被广泛使用。这会引发一个问题:短时间内生成的海量视频数据无法快速处理,从而严重影响数据时效性价值的问题愈来愈严重。文中提出一套基于HBase的分布式处理框架。该框架首先支持多客户端同时上传的视频,然后提取其中出现的人脸,最终建立一个可以保存在内存中的索引表进行查询加速。通过处理客户端上传的含有待查人脸的图像,该框架可以快速定位人脸在上传的视频中出现的位置。针对上述需要实现的功能,文中详细描述了实现该框架各部分中最重要的表的具体设计细节与设计目的,同时简述了人脸查询的具体流程,并从整个集群的角度优化集群的具体方法。最终通过在百万人脸中查询特定的一张来揭示集群性能。实验结果显示,该框架有较好的性能并完全能满足真实需求。

An FPGA Implementation of GF(p) Elliptic Curve Cryptographic Coprocessor

A GF(p) elliptic curve cryptographic coprocessor is proposed and implemented on Field Programmable Gate Array (FPGA). The focus of the coprocessor is on the most critical, complicated and time-consuming point multiplications. The technique of coordinates conversion and fast multiplication algorithm of two large integers are utilized to avoid frequent inversions and to accelerate the field multiplications used in point multiplications. The characteristic of hardware parallelism is considered in the implementation of point multiplications. The coprocessor implemented on XILINX XC2V3000 computes a point multiplication for an arbitrary point on a curve defined over GF(2192?264?1) with the frequency of 10 MHz in 4.40 ms in the average case and 5.74 ms in the worst case. At the same circumstance, the coprocessor implemented on XILINX XC2V4000 takes 2.2 ms in the average case and 2.88 ms in the worst case.

电力大数据平台中HBase的实时性优化方案

近年来,随着大数据场景的兴起,RDBMS由于其自身的扩展性和可用性限制无法满足企业需求。No SQL数据库的出现弥补了传统关系型数据库在大数据领域的不足。No SQL数据库本身具有良好的扩展性、容错性以及实时访问、存储TB级别数据的特点。HBase就是以HDFS和MapReduce为基础的开源No SQL型分布式数据库,它不支持二级索引、事务和批量数据处理时延长等^([1])。本文以HBase和Spark为基础,增加插件使HBase支持SQL语句和二级索引,通过修改Spark源码,提升对HBase数据的本地化计算级别。插件对HBase无侵入、低耦合,支持用户输入SQL语句,把输入字段转化为HBase的列族和列限定符,根据不同的场景选取不同的执行方案。MapReduce计算框架具有计算效率低,无法利用HBase的读写缓存的缺陷^([1]),原始Spark框架不能感知HBase数据分片。本文改进Spark能感知HBase数据分片,对HBase中数据进行高级别本地化计算。最终,将本文设计的系统与业内常用的Hive+HBase方案对比常用SQL消耗的时延^([3])。通过实验得出,本文构建的优化方案在没有缺失HBase的优良特性的基础上加强了部分应用场景的实时性。

A Coprocessor Architecture for 80/112-bit Security Related Applications

We have proposed a flexible coprocessor key-authentication architecture for 80/112-bit security-related applications over GF(2m)field by employing Elliptic-curve Diffie Hellman(ECDH)protocol.Towards flexibility,a serial input/output interface is used to load/produce secret,public,and shared keys sequentially.Moreover,to reduce the hardware resources and to achieve a reasonable time for cryptographic computations,we have proposed a finite field digit-serial multiplier architecture using combined shift and accumulate techniques.Furthermore,two finite-statemachine controllers are used to perform efficient control functionalities.The proposed coprocessor architecture over GF(2^(163))and GF(2^(233))is programmed using Verilog and then implemented on Xilinx Virtex-7 FPGA(field-programmable-gate-array)device.For GF(2^(163))and GF(2^(233)),the proposed flexible coprocessor use 1351 and 1789 slices,the achieved clock frequency is 250 and 235MHz,time for one public key computation is 40.50 and 79.20μs and time for one shared key generation is 81.00 and 158.40μs.Similarly,the consumed power over GF(2^(163))and GF(2^(233))is 0.91 and 1.37mW,respectively.The proposed coprocessor architecture outperforms state-of-the-art ECDH designs in terms of hardware resources.

Hardware-Software Co-implementation of H.264 Decoder in SoC

With the increasing demand for flexible and efficient implementation of image and video processing algorithms, there should be a good tradeoff between hardware and software design method. This paper utilized the HW-SW codesign method to implement the H.264 decoder in an SoC with an ARM core, a multimedia processor and a deblocking filter coprocessor. For the parallel processing features of the multimedia processor, clock cycles of decoding process can be dramatically reduced. And the hardware dedicated deblocking filter coprocessor can improve the efficiency a lot. With maximum clock frequency of 150 MHz, the whole system can achieve real time processing speed and flexibility.

Intel^(■) Math Kernel Library PARDISO* forIntel^(■) Xeon Phi^(TM) Manycore Coprocessor

The paper describes an efficient direct method to solve an equation Ax = b, where A is a sparse matrix, on the Intel®Xeon PhiTM coprocessor. The main challenge for such a system is how to engage all available threads (about 240) and how to reduce OpenMP* synchronization overhead, which is very expensive for hundreds of threads. The method consists of decomposing A into a product of lower-triangular, diagonal, and upper triangular matrices followed by solves of the resulting three subsystems. The main idea is based on the hybrid parallel algorithm used in the Intel®Math Kernel Library Parallel Direct Sparse Solver for Clusters [1]. Our implementation exploits a static scheduling algorithm during the factorization step to reduce OpenMP synchronization overhead. To effectively engage all available threads, a three-level approach of parallelization is used. Furthermore, we demonstrate that our implementation can perform up to 100 times better on factorization step and up to 65 times better in terms of overall performance on the 240 threads of the Intel®Xeon PhiTM coprocessor.

A Novel Defibrillator-Specific Coprocessor Capable of Running Entropy and CNN Integration Algorithms

It is difficult for the existing Automated External Defibrillator (AED) on-board microprocessors to accurately classify electrocardiographic signals (ECGs) mixed with Cardiopulmonary Resuscitation artifacts in real-time. In order to improve recognition speed and accuracy of electrocardiographic signals containing Cardiopulmonary Resuscitation artifacts, a new special coprocessor system-on-chip (SoC) for defibrillators was designed. In this study, a microprocessor was designed based on the RISC-V architecture to achieve hardware acceleration for ECGs classification;Besides, an Approximate Entropy (ApEn) and Convolutional neural networks (CNNs) integrated algorithm capable of running on it was designed. The algorithm differs from traditional electrocardiographic (ECG) classification algorithms. It can be used to perform ECG classification while chest compressions are applied. The proposed co-processor can be used to accelerate computation rate of ApEn by 34 times compared with pure software computation. It can also be used to accelerate the speed of CNNs ECG recognition by 33 times. The combined algorithm was used to classify ECGs with CPR artifacts. It achieved a precision of 96%, which was significantly superior to that of simple CNNs. The coprocessor can be used to significantly improve the recognition efficiency and accuracy of ECGs containing CPR artifacts. It is suitable for automatic external defibrillator and other medical devices in which one-dimensional physiological signals.

Architecture Design of Computing Intensive SoCs

Most existing system-on-chip （SoC） architectures are for microprocessor-centric designs. They are not suitable for computing intensive SoCs, which have their own conflgurability, extendibility, perform- ance, and data exchange characteristics. This paper analyzes these characteristics and gives design princi- ples for computing intensive SoCs. Three architectures suitable for different situations are compared with selection criteria given. The architectural design of a high performance network security accelerator （HPNSA） is used to elaborate on the design techniques to fully exploit the performance potential of the ar- chitectures. A behavior-level simulation system is implemented with the C＋＋ programming language to evaluate the HPNSA performance and to obtain the optimum system design parameters. Simulations show that this architecture provides high performance data transfer.