The implementation of the coordinate rotational digital computer （CORDIC） algorithm with wave pipelining technique on field programmable gate array （FPGA） is described. All data in FPGA-based wave pipelining pass ...The implementation of the coordinate rotational digital computer （CORDIC） algorithm with wave pipelining technique on field programmable gate array （FPGA） is described. All data in FPGA-based wave pipelining pass through a number of logic gates, in the same way that all data pass through the same number of registers in a conventional pipeline. Moreover, all paths are routed using identical routing resources. The manual placement, timing driven routing and timing analyzing techniques are applied to optimize the layout for achieving good path balance. Experimental results show that a 256-LUT logic depth circuit mapped on XC4VLX15-12 runs as high as 330 MHz, whichis a little lower than the speed of 336 MHz based on the conventional 16-stage pipelining in the same chip. The latency of the wave pipelining circuit is 30.3 ns, which is 36.4% shorter than the latency of 16-stage conventional pipelining circuit.展开更多
CORDIC(coordinate rotation digital computing)算法能够通过简单的移位、加减运算得到任意输入角度的正弦或余弦值,具有速度快、精度灵活可调、硬件实现简单等优点。在深入分析CORDIC基本算法原理的基础上,实现了一种改进算法,这种改...CORDIC(coordinate rotation digital computing)算法能够通过简单的移位、加减运算得到任意输入角度的正弦或余弦值,具有速度快、精度灵活可调、硬件实现简单等优点。在深入分析CORDIC基本算法原理的基础上,实现了一种改进算法,这种改进算法的迭代方向由输入角二进制表示时的各位位值直接确定,避免了CORDIC基本算法中迭代方向需由剩余角度计算结果决定的不足,从而提高了CORDIC算法的运行速度,减小了电路规模,并且对算法的综合性能也有一定改善。展开更多
针对基于FPGA的分布式导航系统中涉及大量的三角函数运算,而传统的查找表或差值法计算,在精度、运算速度方面不能兼得,且占用资源多,文中提出了基于CORDIC算法的反正切函数计算的改进方法与流水线结构的实现方法,使用VHDL硬件描述语言...针对基于FPGA的分布式导航系统中涉及大量的三角函数运算,而传统的查找表或差值法计算,在精度、运算速度方面不能兼得,且占用资源多,文中提出了基于CORDIC算法的反正切函数计算的改进方法与流水线结构的实现方法,使用VHDL硬件描述语言进行编程实现,在Quartus II 9.0中对算法进行功能仿真,最后通过Altera公司的FPGA Cyclone II系列芯片进行了具体验证。验证结果表明,针对累加器中因截尾而产生的误差所作的算法改进,显著地提高了算法精度,而且运算速度快。展开更多
文摘The implementation of the coordinate rotational digital computer （CORDIC） algorithm with wave pipelining technique on field programmable gate array （FPGA） is described. All data in FPGA-based wave pipelining pass through a number of logic gates, in the same way that all data pass through the same number of registers in a conventional pipeline. Moreover, all paths are routed using identical routing resources. The manual placement, timing driven routing and timing analyzing techniques are applied to optimize the layout for achieving good path balance. Experimental results show that a 256-LUT logic depth circuit mapped on XC4VLX15-12 runs as high as 330 MHz, whichis a little lower than the speed of 336 MHz based on the conventional 16-stage pipelining in the same chip. The latency of the wave pipelining circuit is 30.3 ns, which is 36.4% shorter than the latency of 16-stage conventional pipelining circuit.
文摘CORDIC(coordinate rotation digital computing)算法能够通过简单的移位、加减运算得到任意输入角度的正弦或余弦值,具有速度快、精度灵活可调、硬件实现简单等优点。在深入分析CORDIC基本算法原理的基础上,实现了一种改进算法,这种改进算法的迭代方向由输入角二进制表示时的各位位值直接确定,避免了CORDIC基本算法中迭代方向需由剩余角度计算结果决定的不足,从而提高了CORDIC算法的运行速度,减小了电路规模,并且对算法的综合性能也有一定改善。
文摘针对基于FPGA的分布式导航系统中涉及大量的三角函数运算,而传统的查找表或差值法计算,在精度、运算速度方面不能兼得,且占用资源多,文中提出了基于CORDIC算法的反正切函数计算的改进方法与流水线结构的实现方法,使用VHDL硬件描述语言进行编程实现,在Quartus II 9.0中对算法进行功能仿真,最后通过Altera公司的FPGA Cyclone II系列芯片进行了具体验证。验证结果表明,针对累加器中因截尾而产生的误差所作的算法改进,显著地提高了算法精度,而且运算速度快。
