Mathematical modeling for dynamic stability of sandwich beam with variable mechanical properties of core

The paper is devoted to mathematical modelling of static and dynamic stability of a simply supported three-layered beam with a metal foam core. Mechanical properties of the core vary along the vertical direction. The field of displacements is for- mulated using the classical broken line hypothesis and the proposed nonlinear hypothesis that generalizes the classical one. Using both hypotheses, the strains are determined as well as the stresses of each layer. The kinetic energy, the elastic strain energy, and the work of load are also determined. The system of equations of motion is derived using Hamilton＇s principle. Finally, the system of three equations is reduced to one equation of motion, in particular, the Mathieu equation. The Bubnov-Galerkin method is used to solve the system of equations of motion, and the Runge-Kutta method is used to solve the second-order differential equation. Numerical calculations are done for the chosen family of beams. The critical loads, unstable regions, angular frequencies of the beam, and the static and dynamic equilibrium paths are calculated analytically and verified numerically. The results of this study are presented in the forms of figures and tables.

Influence of core sand properties on flow dynamics of core shooting process based on experiment and multiphase simulation

The influence of core sand properties on flow dynamics was investigated synchronously with various core sands, transparent core-box and high-speed camera. To confirm whether the core shooting process has significant turbulence, the flow pattern of sand particles in the shooting head and core box was reproduced with colored core sands. By incorporating the kinetic theory of granular flow(KTGF), kinetic-frictional constitutive correlation and turbulence model, a two-fluid model(TFM) was established to study the flow dynamics of the core shooting process. Two-fluid model(TFM) simulations were then performed and a areasonable agreement was achieved between the simulation and experimental results. Based on the experimental and simulation results, the effects of turbulence, sand density, sand diameter and binder ratio were analyzed in terms of filling process, sand volume fraction(αs) and sand velocity(Vs).

Design of IP core for IIC bus controller based on FPGA

The intellectual property （IP） core for inter-integrated circuit （IIC） bus controller is designed using finite state machine （FSM） based on field programmable gate array （FPGA）. Not only the data from AT 24C02C can be read automatically after power on, but also the data from upper computer can be written into AT24C02C immediately under the control of the IIC bus controller. When it is applied to blast wave overpressure test system, the IIC bus controller can read and store working parameters automatically. In a laboratory environment, the IP core simulation is carried out and the result is accurate. In the explosion field test, by analyzing the obtained valid data, it can be concluded that the designed IP core has good reliability.

Design of IP core based on AMBA bus

With the rapid development of integrated circuit(IC)technology,reusable intelligent property(IP)core design is widely valued by the industry.Based on the in-depth study of the functional characteristics of advanced microcontroller bus architecture(AMBA),a design scheme of IP core is presented,and it is divided into the functional modules,and the structural design of the IP core is completed.The relationship between the internal modules of the IP core is clarified,and the top-down design method is used to build the internal architecture of the IP core.The IP core interface module,register module,baud rate module,transmit module,receive module,and interrupt module are designed in detail by using Verilog language.The simulation results show that the designed IP core supports serial peripheral interface(SPI)protocol,the function coverage of IP core reaches 100%,the maximum working frequency reaches 200 MHz,and the resource occupancy rate is less than 15%.The reusable IP core can support multiple data formats,multiple timing transmission modes,and master/slave operation modes,reducing the resource consumption of hardware circuits and having stronger applicability.