A low-power high-quality CMOS image sensor using 1.5 V 4T pinned photodiode and dual-CDS column-parallel single-slope ADC

This paper presents a low-power high-quality CMOS image sensor(CIS)using 1.5 V 4T pinned photodiode(4T-PPD)and dual correlated double sampling(dual-CDS)column-parallel single-slope ADC.A five-finger shaped pixel layer is proposed to solve image lag caused by low-voltage 4T-PPD.Dual-CDS is used to reduce random noise and the nonuniformity between columns.Dual-mode counting method is proposed to improve circuit robustness.A prototype sensor was fabricated using a 0.11μm CMOS process.Measurement results show that the lag of the five-finger shaped pixel is reduced by 80%compared with the conventional rectangular pixel,the chip power consumption is only 36 mW,the dynamic range is 67.3 dB,the random noise is only 1.55 e^(-)_(rms),and the figure-of-merit is only 1.98 e^(-)·nJ,thus realizing low-power and high-quality imaging.

CCD signal acquisition and optimal digital denoise technology

To reduce the charge-coupled device(CCD)readout noise and improve the detection ability under low illumination and dim targets,a new low-noise CCD signal processing technology-CCD digital denoiseis gradually being employed in aerospace detection and other fields.In this study,the main readout noise of CCD detectors and its characteristics are analyzed.A CCD digital denoise system and an experimental platform are designed as well as established by using a PCIe data acquisition card.According to the characteristics of readout noise,some digital filters are analyzed and designed based on distributed kernel coefficient,and the optimal kernel coefficients are obtained through iteration.Then,CCD signal and filter model are established,and the optimal filter is designed to apply to the digital denoise system.Finally,according to the image data obtained from the system,the performance of the digital denoise system and digital filtering algorithm is evaluated and compared.At 500 kHz and 1 MHz CCD readout rates,the denoising performance of the optimal filter designed in the experiment is 16%-32%higher than that of the digital filter with kernel distribution coefficient,and 50%-60%higher than that of the traditional correlated double sampling technology.

A novel switched capacitor bandgap reference with a correlated double sampling structure

A switched capacitor bandgap voltage reference with correlated double sampling structure embedded in a temperature sensor is implemented in a standard 0.35 um CMOS process. Due to the smaller change of the op-amp＇s output voltage, this topology is very suitable for low power applications. In addition, errors caused by the finite op-amp gain, input offset voltage, and 1/f noise are eliminated with the correlated double sampling technique. Additionally, two-level process calibration techniques are designed to minimize the process spread. Finally, a method of getting a full period valid reference voltage output is discussed and experimental results are provided to verify the effectiveness of the proposed structure.

MIXED-GRAINED CMOS FIELD PROGRAMMABLE ANALOG ARRAY FOR SMART SENSORY APPLICATIONS

The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.

Research on high-speed TDICCD remote sensing camera video signal processing

Video signal processing needs high signal-to-noise ratio （SNR） in high-speed time delay and integration charge coupled devices （TDICCD）. To solve this problem, this article first analyzes the characteristics of the output video signal of a new type of high-speed TDICCD and its operation principle. Then it studies the correlation double sample （CDS） method of reducing noise. Following that a synthesized processing method is proposed, including correlation double sample, programmable gain control, line calibration and digital offset control, etc. Among the methods, XRD98L59 is a video signal processor for the charge coupled device （CCD）. Application of this processor to one kind of high-speed TDICCD with eight output ports achieves perfect video images. The experiment result indicates that the SNR of the images reaches about 50 dB. The video signal processing for high-speed multi-channel TDICCD is implemented, which meets the required project index.

An A/D interface based on ∑△ modulator for thermal vacuum sensor ASICs

A newΣΔmodulator architecture for thermal vacuum sensor ASICs is proposed.The micro-hotplate thermal vacuum sensor fabricated by surface-micrornachining technology can detect the gas pressure from 1 to 10;Pa. The amplified differential output voltage signal of the sensor feeds to theΣΔmodulator to be converted into digital domain.The presentedΣΔmodulator makes use of a feed-forward path to suppress the harmonic distortions and attain high linearity.Compared with other feed-forward architectures presented before,the circuit complexity,chip area and power dissipation of the proposed architecture are significantly decreased.The correlated double sampling technique is introduced in the 1st integrator to reduce the flicker noise.The measurement results demonstrate that the modulator achieves an SNDR of 79.7 dB and a DR of 80 dB over a bandwidth of 7.8 kHz at a sampling rate of 4 MHz.The circuit has been fabricated in a 0.5μm 2P3M standard CMOS technology.It occupies an area of 5 mm;and dissipates 9 mW from a single 3 V power supply.The performance of the modulator meets the requirements of the considered application.

A 10-bit column-parallel cyclic ADC for high-speed CMOS image sensors

This paper presents a high-speed column-parallel cyclic analog-to-digital converter（ADC） for a CMOS image sensor.A correlated double sampling（CDS） circuit is integrated in the ADC,which avoids a stand-alone CDS circuit block.An offset cancellation technique is also introduced,which reduces the column fixed-pattern noise（FPN） effectively.One single channel ADC with an area less than 0.02 mm^2 was implemented in a 0.13μm CMOS image sensor process.The resolution of the proposed ADC is 10-bit,and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively.The power consumption from 3.3 V supply is only 0.66 mW.An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels.The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.

A digital CDS technique and its performance testing

Readout noise is a critical parameter for characterizing the performance of charge-coupled devices（CCDs）, which can be greatly reduced by the correlated double sampling（CDS） circuit. However, a conventional CDS circuit inevitably introduces new noise since it consists of several active analog components such as operational amplifiers. This paper proposes a digital CDS circuit technique, which transforms the pre-amplified CCD signal into a train of digital presentations by a high-speed data acquisition card directly without the noisy CDS circuit,then implements the digital CDS algorithm through a numerical method. A readout noise of 3.3 e- and an energy resolution of 121 e V@5.9 ke V can be achieved via the digital CDS technique.