Stochastic Analysis of Interconnect Delay in the Presence of Process Variations

Process variations can reduce the accuracy in estimation of interconnect performance. This work presents a process variation based stochastic model and proposes an effective analytical method to estimate interconnect delay. The technique decouples the stochastic interconnect segments by an improved decoupling method. Combined with a polynomial chaos expression （PCE）, this paper applies the stochastic Galerkin method （SGM） to analyze the system response. A finite representation of interconnect delay is then obtained with the complex approximation method and the bisection method. Results from the analysis match well with those from SPICE. Moreover, the method shows good computational efficiency, as the running time is much less than the SPICE simulation＇s.

FDTD based transition time dependent crosstalk analysis for coupled RLC interconnects

The performance of high density chips operating in the GHz range is mostly affected by on-chip interconnects. The interconnect delay depends on many factors, a few of them are inputs toggling patterns, line ＆ coupling parasitics, input rise/fall time and source/load characteristics. The transition time of the input is of prime importance in high speed circuits. This paper addresses the FDTD based analysis of transition time effects on functional and dynamic crosstalk. The analysis is carried out for equal and unequal transition times of coupled inputs. The analysis of the effects of unequal rise time is equally important because practically, it is quite common to have mismatching in the rise time of the signals transmitting through different length wires. To demonstrate the effects, two distributed RLC lines coupled inductively and capacitively are taken into consideration. The FDTD technique is used because it gives accurate results and carries time domain analysis of coupled lines. The number of lumps in SPICE simulations is considered the same as those of spatial segments. To validate the FDTD computed results, SPICE simulations are run and results are compared. A good agreement of the computed results has been observed with respect to SPICE simulated results. An average error of less than 3.2% is observed in the computation of the performance parameters using the proposed method.

A Novel Interconnect Crosstalk Parallel RLC Analyzable Model Based on the 65nm CMOS Process

Based on the 65nm CMOS process,a novel parallel RLC coupling interconnect analytical model is presented synthetically considering parasitical capacitive and parasitical inductive effects. Applying function approximation and model order-reduction to the model, we derive a closed-form and time-domain waveform for the far-end crosstalk of a victim line under ramp input transition. For various interconnect coupling sizes, the proposed RLC coupling analytical model enables the estimation of the crosstalk voltage within 2.50% error compared with Hspice simulation in a 65nm CMOS process. This model can be used in computer-aided-design of nanometer SOCs.