Critical path tracing,a fault simulation method for gate-level combinational circuits,is extended to theparallel critical path tracing for functional block-level combinational circuits.If the word length of the hostco...Critical path tracing,a fault simulation method for gate-level combinational circuits,is extended to theparallel critical path tracing for functional block-level combinational circuits.If the word length of the hostcomputer is m,then the parallel critical path tracing will be approximately m times faster than the originalone.展开更多
In order to cope with the most expensive stem fault simulation in fault simu-lation field, several accelerated techniques are presented in this paper. These techniques include static analysis on circuit structure in p...In order to cope with the most expensive stem fault simulation in fault simu-lation field, several accelerated techniques are presented in this paper. These techniques include static analysis on circuit structure in preprocessing stage and dynamic calculations in fault simulation stage. With these techniques,the area for stem fault simulation and number of the stems requiring explicit fault simulation are greatly reduced, so that the entire fault simulation time is substantially decreased. Experimental results given in this paper show that the fault simulation algorithm using these techniques is of very high efficiency for both small and large numbers of test patterns. Especially with the increase of circuit gates, its effectivenbss improves obyiously.展开更多
基金The project is supported by the National Natural Science Foundation of China.
文摘Critical path tracing,a fault simulation method for gate-level combinational circuits,is extended to theparallel critical path tracing for functional block-level combinational circuits.If the word length of the hostcomputer is m,then the parallel critical path tracing will be approximately m times faster than the originalone.
文摘In order to cope with the most expensive stem fault simulation in fault simu-lation field, several accelerated techniques are presented in this paper. These techniques include static analysis on circuit structure in preprocessing stage and dynamic calculations in fault simulation stage. With these techniques,the area for stem fault simulation and number of the stems requiring explicit fault simulation are greatly reduced, so that the entire fault simulation time is substantially decreased. Experimental results given in this paper show that the fault simulation algorithm using these techniques is of very high efficiency for both small and large numbers of test patterns. Especially with the increase of circuit gates, its effectivenbss improves obyiously.
