A critical path approach for elucidating the temperature dependence of granular hopping conduction

We revisit the classical problem of granular hopping conduction＇s σ∝exp[-（To/T）1/2] temperature dependence, where a denotes conductivity, T is temperature, and To is a sample-dependent constant. By using the hopping conduction formulation in conjunction with the incorporation of the random potential that has been shown to exist in insulator-conductor composites, it is demonstrated that the widely observed temperature dependence of granular hopping conduction emerges very naturally through the immediate-neighbor critical-path argument. Here, immediate-neighbor pairs are defined to be those where a line connecting two grains does not cross or by-pass other grains, and the critical-path argument denotes the derivation of sample conductance based on the geometric percolation condition that is marked by the critical conduction path in a random granular composite. Simulations based on the exact electrical network evaluation of finite-sample conductance show that the configuration- averaged results agree well with those obtained using the immediate-neighbor critical-path method. Furthermore, the results obtained using both these methods show good agreement with experimental data on hopping conduction in a sputtered metal-insulator composite Agx（SnO2）1-x, where x denotes the metal volume fraction. The present approach offers a relatively straightforward and simple expla- nation for the temperature behavior that has been widely observed over diverse material systems, but which has remained a puzzle in spite of the various efforts made to explain this phenomenon.

Parallel Critical Path Tracing——A Fault Simulation Algorithm for Combinational Circuits

Critical path tracing,a fault simulation method for gate-level combinational circuits,is extended to theparallel critical path tracing for functional block-level combinational circuits.If the word length of the hostcomputer is m,then the parallel critical path tracing will be approximately m times faster than the originalone.

A Complete Critical Path Algorithm for Test Generation of Combinational Circuits

It is known that critical path test generation method is not a complete algorithm for combinational circuits with reconvergent-fanout.In order to make it a complete algorithm,we put forward a reconvergent-fanout- oriented technique,the principal critical path algorithm,propagating the critical value back to primary inputs along a single path,the principal critical path,and allowing multiple path sensitization if needed.Relationship among test patterns is also discussed to accelerate test generation.

Critical Path in Probabilistic Network Model for Financial Planning

In this paper, a probabilistic network model for financial planning is proposed. The optimum value of the objective function of the model is evaluated by its expected value. However,calculating the expected argue of optimum argue is NP-hard. In the paper, the concept of critical path is given, and the method locating the expected solution to the unit cash now problem is provided.

Reliable Failure Restoration with Bayesian Congestion Aware for Software Defined Networks

SoftwareDefined Networks(SDN)introduced better network management by decoupling control and data plane.However,communication reliability is the desired property in computer networks.The frequency of communication link failure degrades network performance,and service disruptions are likely to occur.Emerging network applications,such as delaysensitive applications,suffer packet loss with higher Round Trip Time(RTT).Several failure recovery schemes have been proposed to address link failure recovery issues in SDN.However,these schemes have various weaknesses,which may not always guarantee service availability.Communication paths differ in their roles;some paths are critical because of the higher frequency usage.Other paths frequently share links between primary and backup.Rerouting the affected flows after failure occurrences without investigating the path roles can lead to post-recovery congestion with packet loss and system throughput.Therefore,there is a lack of studies to incorporate path criticality and residual path capacity to reroute the affected flows in case of link failure.This paper proposed Reliable Failure Restoration with Congestion Aware for SDN to select the reliable backup path that decreases packet loss and RTT,increasing network throughput while minimizing post-recovery congestion.The affected flows are redirected through a path with minimal risk of failure,while Bayesian probability is used to predict post-recovery congestion.Both the former and latter path with a minimal score is chosen.The simulation results improved throughput by(45%),reduced packet losses(87%),and lowered RTT(89%)compared to benchmarking works.

Emergency Local Searching Approach for Job Shop Scheduling

Existing methods of local search mostly focus on how to reach optimal solution.However,in some emergency situations,search time is the hard constraint for job shop scheduling problem while optimal solution is not necessary.In this situation,the existing method of local search is not fast enough.This paper presents an emergency local search(ELS) approach which can reach feasible and nearly optimal solution in limited search time.The ELS approach is desirable for the aforementioned emergency situations where search time is limited and a nearly optimal solution is sufficient,which consists of three phases.Firstly,in order to reach a feasible and nearly optimal solution,infeasible solutions are repaired and a repair technique named group repair is proposed.Secondly,in order to save time,the amount of local search moves need to be reduced and this is achieved by a quickly search method named critical path search(CPS).Finally,CPS sometimes stops at a solution far from the optimal one.In order to jump out the search dilemma of CPS,a jump technique based on critical part is used to improve CPS.Furthermore,the schedule system based on ELS has been developed and experiments based on this system completed on the computer of Intel Pentium(R) 2.93 GHz.The experimental result shows that the optimal solutions of small scale instances are reached in 2 s,and the nearly optimal solutions of large scale instances are reached in 4 s.The proposed ELS approach can stably reach nearly optimal solutions with manageable search time,and can be applied on some emergency situations.

Penalty model for delay of bidding section construction period in South-to-North Water Diversion Eastern Route Project from perspective of programs

According to the multi-project and program management theory, this paper analyzes the program generation principle and establishes a program based on progress goals. On the basis of the present situation of calculation of penalty for delay of the bidding section construction period with the critical path method, we studied the effects of contractor-induced delay of the bidding section construction period in detail, including the effects on the construction period of the bidding section itself, the earliest start times of the next bidding section and other subsequent bidding sections, and the construction period of the program, and then constructed a penalty model for delay of the bidding section construction period from the perspective of programs. Using the penalty model, we conducted a practical analysis of penalty for delay of the construction period of the Baoying station program in the South-to-North Water Diversion Project. The model can help determine the amount of penalty for delay of the construction period in bidding sections scientifically and reasonably,

RESEARCH ON THE PACKING ALGORITHM FOR ANTI-SEU OF FPGA BASED ON TRIPLE MODULAR REDUNDANCY AND THE NUMBERS OF FAN-OUTS OF THE NET

Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-FPGA SEU capability, the registers of the circuit netlist are tripled and divided into three categories in this study. By the packing algorithm, the registers of triple modular redundancy are loaded into different configurable logic block. At the same time, the packing algorithm considers the effect of large fan-out nets. The experimental results show that the algorithm successfully realize the packing of the register of Triple Modular Redundancy(TMR). Comparing with Timing Versatile PACKing(TVPACK), the algorithm in this study is able to obtain a 11% reduction of the number of the nets in critical path, and a 12% reduction of the time delay in critical path on average when TMR is not considered. Especially, some critical path delay of circuit can be improved about 33%.

PERT and CPM in Project Management with Practical Examples

This paper reviewed the concepts of Project Evaluation Review Technique and Critical Path Method in project management with practical examples. The methods and success of quantitative decision-making approaches in project management through the use of project evaluation review technique and the critical path method as regards project duration and critical activities of a project, were discussed. The review found that while both methods are effective in achieving success in project management, the relationship and connectivity of activities involved in a project life cycle are key aspects. The paper concludes that the project evaluation review technique is more effective when the duration of the project is uncertain, while the critical path method is effective when the project’s end time is certain. The paper, therefore, recommends that to achieve maximum operative efficiency in utilizing resources in project management, prior to commencing the execution of a project, all required resources to cover every activity must be assembled and prioritized to eliminate interruptions that could bring delay and unnecessary cost implications. Again, policies focused on improving project execution should be implemented in developing nations to minimize the many cases of failed and delayed projects. Subsequently, stakeholders in projects must be given the right, under the law, to prosecute the government, its agencies and/or the executors of projects for failure to execute a project on schedule.

A novel BIST scheme for circuit aging measurement of aerospace chips

The avionics working environment is bad, easy to accelerate aging of circuits. Circuit aging is one of the important factors that influence the reliability of avionics, so circuit aging testing is of great significance to improve the reliability of avionics. As continuing aging would degrade circuit performance, aging can be monitored through precise measurement of performance degradation. However, previous methods for predicting circuit performance have limited prediction accuracy. In this paper, we propose a novel Built-In Self-Test（BIST） scheme for circuit aging measurement, which constructs self-oscillation loops employing parts of critical paths and activates oscillations by specific test patterns. An aging signature counter is then used to capture the oscillation frequency and in turn measure the aging state of the circuit. We propose to implement this measurement process by BIST. Experimental results show that the proposed in-field aging measurement is robust with respect to process variations and can achieve a precision of about 90%. The application of this scheme has a certain value to improve the reliability of avionics systems.

Accelerated Techniques in Stem Fault Simulation

In order to cope with the most expensive stem fault simulation in fault simu-lation field, several accelerated techniques are presented in this paper. These techniques include static analysis on circuit structure in preprocessing stage and dynamic calculations in fault simulation stage. With these techniques,the area for stem fault simulation and number of the stems requiring explicit fault simulation are greatly reduced, so that the entire fault simulation time is substantially decreased. Experimental results given in this paper show that the fault simulation algorithm using these techniques is of very high efficiency for both small and large numbers of test patterns. Especially with the increase of circuit gates, its effectivenbss improves obyiously.