Bifurcation and chaos in high-frequency peak current mode Buck converter working in continuous conduction mode（CCM） are studied in this paper. First of all, the two-dimensional discrete mapping model is established....Bifurcation and chaos in high-frequency peak current mode Buck converter working in continuous conduction mode（CCM） are studied in this paper. First of all, the two-dimensional discrete mapping model is established. Next, reference current at the period-doubling point and the border of inductor current are derived. Then, the bifurcation diagrams are drawn with the aid of MATLAB. Meanwhile, circuit simulations are executed with PSIM, and time domain waveforms as well as phase portraits in i_L–v_C plane are plotted with MATLAB on the basis of simulation data. After that, we construct the Jacobian matrix and analyze the stability of the system based on the roots of characteristic equations. Finally, the validity of theoretical analysis has been verified by circuit testing. The simulation and experimental results show that,with the increase of reference current I_（ref）, the corresponding switching frequency f is approaching to low-frequency stage continuously when the period-doubling bifurcation happens, leading to the converter tending to be unstable. With the increase of f, the corresponding Irefdecreases when the period-doubling bifurcation occurs, indicating the stable working range of the system becomes smaller.展开更多
To improve the power sequencing performance of the system-on-a-chip（SOC）,a novel embedded soft-start circuit is presented.A seamless soft-start reference voltage is obtained with 7 bits DAC,which can not only restra...To improve the power sequencing performance of the system-on-a-chip（SOC）,a novel embedded soft-start circuit is presented.A seamless soft-start reference voltage is obtained with 7 bits DAC,which can not only restrain the turning point overshoot,but also improve the output accuracy and the poor loading capability,reduce the pin number and save PCB area.The whole DC-DC converter has been fabricated in a 0.35μm CMOS process.The measurement results show that the chip starts up successfully with 250μs soft-start time under conditions of 400 kHz switching frequency,2.5 V DC-DC output and 1.8 V LDO output.Stable operation after soft-start is also shown.展开更多
This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,th...This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,the PGA occupies 0.39 mm2 die area and dissipates 6.5 mW power from a 1.2 V power supply.By using a single loop single digital-to-analog converter（DAC） mixed signal DC offset cancellation topology,the minimum DCOC settling time achieved is as short as 1.6μs with the PGA gain ranging from -8 to 54 dB in a 2 dB step.The DCOC loop utilizes a segmented DAC structure to lower the design complexity without sacrificing accuracy and a digital control algorithm to dynamically set the DCOC loop to fast or normal response mode,making the PGA circuit in compliance with the targeted WLAN specifications.展开更多
基金Project supported by the National Natural Science Foundation of China(Grant No.61376029)the Fundamental Research Funds for the Central Universities,Chinathe College Graduate Research and Innovation Program of Jiangsu Province,China(Grant No.SJLX15 0092)
文摘Bifurcation and chaos in high-frequency peak current mode Buck converter working in continuous conduction mode（CCM） are studied in this paper. First of all, the two-dimensional discrete mapping model is established. Next, reference current at the period-doubling point and the border of inductor current are derived. Then, the bifurcation diagrams are drawn with the aid of MATLAB. Meanwhile, circuit simulations are executed with PSIM, and time domain waveforms as well as phase portraits in i_L–v_C plane are plotted with MATLAB on the basis of simulation data. After that, we construct the Jacobian matrix and analyze the stability of the system based on the roots of characteristic equations. Finally, the validity of theoretical analysis has been verified by circuit testing. The simulation and experimental results show that,with the increase of reference current I_（ref）, the corresponding switching frequency f is approaching to low-frequency stage continuously when the period-doubling bifurcation happens, leading to the converter tending to be unstable. With the increase of f, the corresponding Irefdecreases when the period-doubling bifurcation occurs, indicating the stable working range of the system becomes smaller.
文摘To improve the power sequencing performance of the system-on-a-chip（SOC）,a novel embedded soft-start circuit is presented.A seamless soft-start reference voltage is obtained with 7 bits DAC,which can not only restrain the turning point overshoot,but also improve the output accuracy and the poor loading capability,reduce the pin number and save PCB area.The whole DC-DC converter has been fabricated in a 0.35μm CMOS process.The measurement results show that the chip starts up successfully with 250μs soft-start time under conditions of 400 kHz switching frequency,2.5 V DC-DC output and 1.8 V LDO output.Stable operation after soft-start is also shown.
文摘This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,the PGA occupies 0.39 mm2 die area and dissipates 6.5 mW power from a 1.2 V power supply.By using a single loop single digital-to-analog converter（DAC） mixed signal DC offset cancellation topology,the minimum DCOC settling time achieved is as short as 1.6μs with the PGA gain ranging from -8 to 54 dB in a 2 dB step.The DCOC loop utilizes a segmented DAC structure to lower the design complexity without sacrificing accuracy and a digital control algorithm to dynamically set the DCOC loop to fast or normal response mode,making the PGA circuit in compliance with the targeted WLAN specifications.
