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1.5μm, 8×12.5Gb/s of hybrid-integrated TOSA with isolators and ROSA for 100GbE application 被引量:1
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作者 赵泽平 刘宇 +3 位作者 张志珂 陈向飞 刘建国 祝宁华 《Chinese Optics Letters》 SCIE EI CAS CSCD 2016年第12期45-49,共5页
Compact transmitter and receiver optical sub-assemblies(TOSA and ROSA) are fabricated in our laboratory and have an aggregated capacity of 100 Gb/s. Specially, directly modulated laser(DML) drivers with two layers... Compact transmitter and receiver optical sub-assemblies(TOSA and ROSA) are fabricated in our laboratory and have an aggregated capacity of 100 Gb/s. Specially, directly modulated laser(DML) drivers with two layers of electrical circuit boards are designed to inject RF signals and bias currents separately. For all the lanes, the3 dB bandwidth of the cascade of the TOSA and ROSA exceeds 9 GHz, which allows the 12.5 Gb/s operation.With the 12.5 Gb/s × 8-lane operation, clear eye diagrams for back-to-back and 30-km amplified transmission with a dispersion compensation fiber are achieved. Low cost and simple processing technology make it possible to realize commercial production. 展开更多
关键词 transmitter receiver modulated crosstalk currents compensation aggregated bandwidth cascade separately
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A programmable gain amplifier with digitally assisted DC offset calibration for a direct-conversion WLAN receiver 被引量:1
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作者 姚小城 龚正 石寅 《Journal of Semiconductors》 EI CAS CSCD 2012年第11期90-94,共5页
This paper presents a programmable gain amplifier(PGA) circuit with a digitally assisted DC offset cancellation(DCOC) scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,th... This paper presents a programmable gain amplifier(PGA) circuit with a digitally assisted DC offset cancellation(DCOC) scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,the PGA occupies 0.39 mm2 die area and dissipates 6.5 mW power from a 1.2 V power supply.By using a single loop single digital-to-analog converter(DAC) mixed signal DC offset cancellation topology,the minimum DCOC settling time achieved is as short as 1.6μs with the PGA gain ranging from -8 to 54 dB in a 2 dB step.The DCOC loop utilizes a segmented DAC structure to lower the design complexity without sacrificing accuracy and a digital control algorithm to dynamically set the DCOC loop to fast or normal response mode,making the PGA circuit in compliance with the targeted WLAN specifications. 展开更多
关键词 direct conversion receiver digital assisted DC offset cancellation segmented current mode digital-to-analog converter settling time
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