Novel Perturbation-Immune All-Fiber Optical Architecture for Current Sensing

This paper describes a novel all-fiber optical architecture for electric current or magnetic field sensing which is immune against temperature and vibration perturbations in a hazardous environment. The architecture is structured by employing the fiber-optic wave plates (quarter, half or full) of the patented invention of the senior author. Experimental results on prototype fiber-optic specimen and on a variety of optical fiber networks confirm the respective theoretical predictions.

Charge transfer on porous silicon membranes studied by current-sensing atomic force microscopy

A visible rectification effect on the current-voltage curves of metal/porous silicon/p-silicon has been observed by current-sensing atomic force microscopy. The current-voltage curves of porous silicon membranes with different porosities, prepared through variation of etching current density for a constant time, indicate that a higher porosity results in a higher resistance and thus a lower rectification, until the current reaches a threshold at a porosity 〉55%. We propose that the conductance mode in the porous silicon membrane with porosities 〉55% is mainly a hopping mechanism between nano-crystallites and an inverse static electric field between the porous silicon and p-Si interface blocks the electron injection from porous silicon to p-Si, but with porosities ≤55%, electron flows through a direct continuous channel between nano-crystallites.

Analysis and optimization of current sensing circuit for deep sub-micron SRAM

A quantitative yield analysis of a traditional current sensing circuit considering the random dopant fluctuation effect is presented. It investigates the impact of transistor size, falling time of control signal CS and threshold voltage of critical transistors on failure probability of current sensing circuit. On this basis, we present a final optimization to improve the reliability of current sense amplifier. Under 90 nm process, simulation shows that failure probability of current sensing circuit can be reduced by 80% after optimization compared with the normal situation and the delay time only increases marginally.

Buck Converter Current Measurement Using Differential Amplifier

The accuracy of the measured current is a preeminent parameter for Current Control based Power Converter applications to ensure genuine operation of the designed converter.The current measurement accuracy can be affected by several parameters which includes the type of technology used,components used for the selected technology,aging,usage,operating and environmental conditions.The effect of gain resistors and their manufacturing tolerances on differential amplifier-based buck converter current measurement is investigated in this work.The analysis mainly focused on the output voltage variation and its accuracy with respect to the change in gain resistance tolerances.The gain resistors with 5%,1%,0.5%and 0.1%manufacturing tolerances taken for the worst-case analysis and the calculated performance results are compared and verified with the simula-tion results.The Operational amplifiers(Op-Amp)for high frequency power con-verter applications must operate in a high frequency noise environment and the intended current measuring system must manage common mode noise distur-bances paired with the signal to be measured.Based on the Common Mode Rejec-tion Ratio(CMRR)the common mode voltages and noise signals will effectively getfiltered out.Lesser CMRR results in lower common mode signal rejection,resulting in poor precision and noise rejection.In differential amplifiers,the CMRR predominantly depends on gain resistors.So,the variations in Common Mode Rejection Ratio due to gain resistor tolerances also analyzed and compared with the output voltage variations.Besides the effects of resistor tolerances,this paper also examines the effect of Op-Amp offset voltage on output accuracy spe-cifically for low magnitude input currents.The obtained results from this analysis clearly shows that the gain resistors with 0.1%tolerance gives maximum accuracy with improved CMRR and accuracy at low magnitude input currents will get well improved by using Op-Amps with Low Offset voltage specifications.

Cache Memory Design for Single Bit Architecture with Different Sense Amplifiers

Most modern microprocessors have one or two levels of on-chip caches to make things run faster,but this is not always the case.Most of the time,these caches are made of static random access memory cells.They take up a lot of space on the chip and use a lot of electricity.A lot of the time,low power is more important than several aspects.This is true for phones and tablets.Cache memory design for single bit architecture consists of six transistors static random access memory cell,a circuit of write driver,and sense amplifiers(such as voltage differential sense amplifier,current differential sense amplifier,charge transfer differential sense amplifier,voltage latch sense amplifier,and current latch sense amplifier,all of which are compared on different resistance values in terms of a number of transistors,delay in sensing and consumption of power.The conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34μW of power which shows that power is reduced up to 83%,77.75%reduction in the case of the current differential sense amplifier,39.62%in case of charge transfer differential sense amplifier and 50%in case of voltage latch sense amplifier when compared to existing latch sense amplifier architecture.Furthermore,power reduction techniques are applied over different blocks of cache memory architecture to optimize energy.The single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078μW of power,i.e.,reduce 28%more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.

A low-voltage sense amplifier with two-stage operational amplifier clamping for flash memory

A low-voltage sense amplifier with reference current generator utilizing two-stage operational amplifier clamp structure for flash memory is presented in this paper,capable of operating with minimum supply voltage at1 V.A new reference current generation circuit composed of a reference cell and a two-stage operational amplifier clamping the drain pole of the reference cell is used to generate the reference current,which avoids the threshold limitation caused by current mirror transistor in the traditional sense amplifier.A novel reference voltage generation circuit using dummy bit-line structure without pull-down current is also adopted,which not only improves the sense window enhancing read precision but also saves power consumption.The sense amplifier was implemented in a flash realized in 90 run flash technology.Experimental results show the access time is 14.7 ns with power supply of 1.2 V and slow corner at 125℃.

A low noise high efficiency buck DC-DC converter with sigma-delta modulation

Some research efforts to improve the efficiency and noise performance of buck DC-DC converters are explored.A carefully designed power MOSFET driver,including a dead time controller,discontinuous current mode（DCM） controller and gate width controller,is proposed to improve efficiency.Instead of PWM modulation, sigma-delta modulation is introduced into the feedback loop of the converter to move out the clock-referred harmonic spike.The proposed converter has been designed and fabricated by a 0.35μm CMOS process.Measured results show that the peak efficiency of the converter can reach 93%and sigma-delta modulation suppresses the harmonic spike by 30 dB over PWM modulation.