By applying switch-signal theory, the interaction between MOS transmission switch-ing transistor and current signal in current-mode CMOS circuits is analyzed, and the theory oftransmission current-switches which is su...By applying switch-signal theory, the interaction between MOS transmission switch-ing transistor and current signal in current-mode CMOS circuits is analyzed, and the theory oftransmission current-switches which is suitable to current-mode CMOS circuits is proposed. Thecircuits, such as ternary full-adder etc., designed by using this theory have simpler circuit struc-tures and correct logic functions. It is confirmed that this theory is efficient in guiding the logicdesign of current-mode CMOS circuits at switch level.展开更多
By applying switch-signal theory, the theory of transmission current-switches based on symmetric ternary logic is proposed, this theory is suitable to design symmetric ternary current-mode CMOS circuits. The symmetric...By applying switch-signal theory, the theory of transmission current-switches based on symmetric ternary logic is proposed, this theory is suitable to design symmetric ternary current-mode CMOS circuits. The symmetric ternary current-mode CMOS circuits designed by using this theory not only have simpler circuit structures and correct logic functions, but also can process bidirectional signals.展开更多
Based on the analysis of the basic principle of slope compensation, a high-precision adaptive slope compensation circuit for peak current mode boost DC/DC converter is designed. The circuit dynamically detects the inp...Based on the analysis of the basic principle of slope compensation, a high-precision adaptive slope compensation circuit for peak current mode boost DC/DC converter is designed. The circuit dynamically detects the input and output voltage of the boost circuit to realize automatic adjustment of the compensation amount with the change of duty ratio, which makes the ramp compensation slope optimized. The design uses a high-precision subtracter to improve the accuracy of slope compensation. While eliminating sub-slope oscillation and improving the stability of boost circuit, the negative impact of compensation on boost circuit is minimized, and the load capacity and transient response speed of boost circuit are guaranteed. The circuit is designed based on SMIC 0.18um CMOS technology, with simple structure, high reliability and easy engineering implementation. Spectre circuit simulator 17.1.0.124 64b simulation results show that the circuit has high compensation accuracy and wide input and output voltage range. When the working voltage is 3.3 V, the compensation slope can be adjusted adaptively under different duty cycles, and the minimum error between the compensation slope and the theoretical optimal compensation slope is only 0.42%.展开更多
电流型电路具有功耗低、速度快的特点,是当今集成电路研究的一个热点.文章基于阈算术代数系统,改进了非相交分解算法;设计了电流型互补金属氧化物半导体(complementary metal oxide semiconductor, CMOS)的异或门电路,并利用改进后的新...电流型电路具有功耗低、速度快的特点,是当今集成电路研究的一个热点.文章基于阈算术代数系统,改进了非相交分解算法;设计了电流型互补金属氧化物半导体(complementary metal oxide semiconductor, CMOS)的异或门电路,并利用改进后的新算法,将n变量函数分解成3变量函数,实现了任意n变量函数电路.模拟测试证明所设计的电路结构简单,且具有正确的逻辑功能.展开更多
This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)tr...This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)transistor level design where MOSFET transistors operating in the saturation region are adopted.The proposed CAB architecture is designed to implement six of thewidely used current mode operations in analog processing systems:addition,subtraction,integration,multiplication,division,and pass operation.The functionality of the proposed CAB is demonstrated through these six operations,where each operation is chosen based on the user’s selection in the CAB interface system.The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations.Furthermore,optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells.Moreover,these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design.Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35μm standard CMOS technology.The design uses a±1.5 V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 mm2.This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article.Consequently,the proposed design has a clear aspect of simplicity,low power consumption,and high bandwidth operation,which makes it a suitable candidate for mobile telecommunications applications.展开更多
The present work deals with 12-bit Nyquist current-steering CMOS digital-to-analog converter (DAC) which is an essential part in baseband section of wireless transmitter circuits. Using oversampling ratio (OSR) for th...The present work deals with 12-bit Nyquist current-steering CMOS digital-to-analog converter (DAC) which is an essential part in baseband section of wireless transmitter circuits. Using oversampling ratio (OSR) for the proposed DAC leads to avoid use of an active analog reconstruction filter. The optimum segmentation (75%) has been used to get the best DNL and reduce glitch energy. This segmentation ratio guarantees the monotonicity. Higher performance is achieved using a new 3-D thermometer decoding method which reduces the area, power consumption and the number of control signals of the digital section. Using two digital channels in parallel, helps reach 1-GSample/s frequency. Simulation results show that the spurious- free-dynamic-range (SFDR) in Nyquist rate is better than 64 dB for sampling frequency up to 1-GSample/s. The analog voltage supply is 3.3 V while the digital part of the chip operates with only 2.4 V. Total power consumption in Nyquist rate measurement is 144.9 mW. The chip has been processed in a standard 0.35 μm CMOS technology. Active area of chip is 1.37 mm2.展开更多
In the field of analog VLSI design, current conveyors have reasonably established their identity as an important circuit design element. In the literature published during the past few years, numerous application have...In the field of analog VLSI design, current conveyors have reasonably established their identity as an important circuit design element. In the literature published during the past few years, numerous application have been reported which are based on a variety of current conveyors. In this paper, an oscillator circuit has been proposed. This oscillator is designed using a single positive type second generation current controlled current conveyor (CCCII+). A CCCII has parasitic input resistance on it’s current input node. This resistance could be exploited to reduce circuit complexities. Thus in this accord, a novel oscillator circuit is proposed which utilizes the parasitic resistance of the CCCII+ along with a few more passive components.展开更多
This paper investigates the issue of testing Current Mode Logic (CML) gates. A three-bit parity checker is used as a case study. It is first shown that, as expected, the stuck-at fault model is not appropriate for tes...This paper investigates the issue of testing Current Mode Logic (CML) gates. A three-bit parity checker is used as a case study. It is first shown that, as expected, the stuck-at fault model is not appropriate for testing CML gates. It is then proved that switching the order in which inputs are applied to a gate will affect the minimum test set;this is not the case in conventional voltage mode gates. Both the circuit output and its inverse have to be monitored to reduce the size of the test set.展开更多
Approximation techniques are useful for implementing pattern recognizers, communication decoders and sensory processing algorithms where computational precision is not critical to achieve the desired system level perf...Approximation techniques are useful for implementing pattern recognizers, communication decoders and sensory processing algorithms where computational precision is not critical to achieve the desired system level performance. In our previous work, we had proposed margin propagation (MP) as an efficient piece-wise linear (PWL) approximation technique to a log-sum-exp function and had demonstrated its advantages for implementing probabilistic decoders. In this paper, we present a systematic and a generalized approach for synthesizing analog piecewise-linear (PWL) computing circuits using the MP principle. MP circuits use only addition, subtraction and threshold operations and hence can be implemented using universal conservation principles like the Kirchoff's current law. Thus, unlike the conventional translinear CMOS current-mode circuits, the operation of the MP circuits are functionally similar in weak, moderate and strong inversion regimes of the MOS transistor making the design approach bias-scalable. This paper presents measured results from MP circuits prototyped in a 0.5μm standard CMOS process verifying the bias-scalable property. As an example, we apply the synthesis approach towards designing linear classifiers and verify its performance using measured results.展开更多
基金Supported by National Natural Science Foundation of China
文摘By applying switch-signal theory, the interaction between MOS transmission switch-ing transistor and current signal in current-mode CMOS circuits is analyzed, and the theory oftransmission current-switches which is suitable to current-mode CMOS circuits is proposed. Thecircuits, such as ternary full-adder etc., designed by using this theory have simpler circuit struc-tures and correct logic functions. It is confirmed that this theory is efficient in guiding the logicdesign of current-mode CMOS circuits at switch level.
基金National Natural Science Foundation of ChinaNatural science Foundation of Zhejiang Province
文摘By applying switch-signal theory, the theory of transmission current-switches based on symmetric ternary logic is proposed, this theory is suitable to design symmetric ternary current-mode CMOS circuits. The symmetric ternary current-mode CMOS circuits designed by using this theory not only have simpler circuit structures and correct logic functions, but also can process bidirectional signals.
文摘Based on the analysis of the basic principle of slope compensation, a high-precision adaptive slope compensation circuit for peak current mode boost DC/DC converter is designed. The circuit dynamically detects the input and output voltage of the boost circuit to realize automatic adjustment of the compensation amount with the change of duty ratio, which makes the ramp compensation slope optimized. The design uses a high-precision subtracter to improve the accuracy of slope compensation. While eliminating sub-slope oscillation and improving the stability of boost circuit, the negative impact of compensation on boost circuit is minimized, and the load capacity and transient response speed of boost circuit are guaranteed. The circuit is designed based on SMIC 0.18um CMOS technology, with simple structure, high reliability and easy engineering implementation. Spectre circuit simulator 17.1.0.124 64b simulation results show that the circuit has high compensation accuracy and wide input and output voltage range. When the working voltage is 3.3 V, the compensation slope can be adjusted adaptively under different duty cycles, and the minimum error between the compensation slope and the theoretical optimal compensation slope is only 0.42%.
文摘电流型电路具有功耗低、速度快的特点,是当今集成电路研究的一个热点.文章基于阈算术代数系统,改进了非相交分解算法;设计了电流型互补金属氧化物半导体(complementary metal oxide semiconductor, CMOS)的异或门电路,并利用改进后的新算法,将n变量函数分解成3变量函数,实现了任意n变量函数电路.模拟测试证明所设计的电路结构简单,且具有正确的逻辑功能.
基金This work was supported in part by the Geran Galakan Penyelidik Muda Grant(GGPM),Universiti Kebangsaan Malaysia,Selangor,Malaysia under grant GGPM-2021-055.
文摘This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)transistor level design where MOSFET transistors operating in the saturation region are adopted.The proposed CAB architecture is designed to implement six of thewidely used current mode operations in analog processing systems:addition,subtraction,integration,multiplication,division,and pass operation.The functionality of the proposed CAB is demonstrated through these six operations,where each operation is chosen based on the user’s selection in the CAB interface system.The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations.Furthermore,optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells.Moreover,these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design.Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35μm standard CMOS technology.The design uses a±1.5 V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 mm2.This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article.Consequently,the proposed design has a clear aspect of simplicity,low power consumption,and high bandwidth operation,which makes it a suitable candidate for mobile telecommunications applications.
文摘The present work deals with 12-bit Nyquist current-steering CMOS digital-to-analog converter (DAC) which is an essential part in baseband section of wireless transmitter circuits. Using oversampling ratio (OSR) for the proposed DAC leads to avoid use of an active analog reconstruction filter. The optimum segmentation (75%) has been used to get the best DNL and reduce glitch energy. This segmentation ratio guarantees the monotonicity. Higher performance is achieved using a new 3-D thermometer decoding method which reduces the area, power consumption and the number of control signals of the digital section. Using two digital channels in parallel, helps reach 1-GSample/s frequency. Simulation results show that the spurious- free-dynamic-range (SFDR) in Nyquist rate is better than 64 dB for sampling frequency up to 1-GSample/s. The analog voltage supply is 3.3 V while the digital part of the chip operates with only 2.4 V. Total power consumption in Nyquist rate measurement is 144.9 mW. The chip has been processed in a standard 0.35 μm CMOS technology. Active area of chip is 1.37 mm2.
文摘In the field of analog VLSI design, current conveyors have reasonably established their identity as an important circuit design element. In the literature published during the past few years, numerous application have been reported which are based on a variety of current conveyors. In this paper, an oscillator circuit has been proposed. This oscillator is designed using a single positive type second generation current controlled current conveyor (CCCII+). A CCCII has parasitic input resistance on it’s current input node. This resistance could be exploited to reduce circuit complexities. Thus in this accord, a novel oscillator circuit is proposed which utilizes the parasitic resistance of the CCCII+ along with a few more passive components.
文摘This paper investigates the issue of testing Current Mode Logic (CML) gates. A three-bit parity checker is used as a case study. It is first shown that, as expected, the stuck-at fault model is not appropriate for testing CML gates. It is then proved that switching the order in which inputs are applied to a gate will affect the minimum test set;this is not the case in conventional voltage mode gates. Both the circuit output and its inverse have to be monitored to reduce the size of the test set.
基金Supported by a Research Grant from The National Science Foundation(CCF:0728996)
文摘Approximation techniques are useful for implementing pattern recognizers, communication decoders and sensory processing algorithms where computational precision is not critical to achieve the desired system level performance. In our previous work, we had proposed margin propagation (MP) as an efficient piece-wise linear (PWL) approximation technique to a log-sum-exp function and had demonstrated its advantages for implementing probabilistic decoders. In this paper, we present a systematic and a generalized approach for synthesizing analog piecewise-linear (PWL) computing circuits using the MP principle. MP circuits use only addition, subtraction and threshold operations and hence can be implemented using universal conservation principles like the Kirchoff's current law. Thus, unlike the conventional translinear CMOS current-mode circuits, the operation of the MP circuits are functionally similar in weak, moderate and strong inversion regimes of the MOS transistor making the design approach bias-scalable. This paper presents measured results from MP circuits prototyped in a 0.5μm standard CMOS process verifying the bias-scalable property. As an example, we apply the synthesis approach towards designing linear classifiers and verify its performance using measured results.
