An improved low distortion sigma-delta ADC（analog-to-digital converter） for wireless local area network standards is presented.A feed-forward MASH 2-2 multi-bit cascaded sigma-delta ADC is adopted; however,this work...An improved low distortion sigma-delta ADC（analog-to-digital converter） for wireless local area network standards is presented.A feed-forward MASH 2-2 multi-bit cascaded sigma-delta ADC is adopted; however,this work shows a much better performance than the ADCs which have been presented to date by adding a feedback factor in the second stage to improve the performance of the in-band SNDR（signal to noise and distortion ratio）,using 4-bit ADCs in both stages to minimize the quantization noise.Data weighted averaging technology is therefore used to decrease the mismatch noise induced by the 4-bit DACs,which improves the SFDR（spurious free dynamic range） of the ADC. The modulator has been implemented by a 0.18μm CMOS process and operates at a single 1.8 V supply voltage. Experimental results show that for a 1.25 MHz @-6 dBFS input signal at 160 MHz sampling frequency,the improved ADC with all non-idealities considered achieves a peak SNDR of 80.9 dB and an SFDR of 87 dB,and the effective number of bits is 13.15 bits.展开更多
基金supported by National Natural Science Foundation of the China(Nos.60725415,60971066 )the National High-Tech Programs of China(Nos.2009AA01Z258,2009AA01Z260)
文摘An improved low distortion sigma-delta ADC（analog-to-digital converter） for wireless local area network standards is presented.A feed-forward MASH 2-2 multi-bit cascaded sigma-delta ADC is adopted; however,this work shows a much better performance than the ADCs which have been presented to date by adding a feedback factor in the second stage to improve the performance of the in-band SNDR（signal to noise and distortion ratio）,using 4-bit ADCs in both stages to minimize the quantization noise.Data weighted averaging technology is therefore used to decrease the mismatch noise induced by the 4-bit DACs,which improves the SFDR（spurious free dynamic range） of the ADC. The modulator has been implemented by a 0.18μm CMOS process and operates at a single 1.8 V supply voltage. Experimental results show that for a 1.25 MHz @-6 dBFS input signal at 160 MHz sampling frequency,the improved ADC with all non-idealities considered achieves a peak SNDR of 80.9 dB and an SFDR of 87 dB,and the effective number of bits is 13.15 bits.
