A 6.25 Gbps SerDes core used in the high signed based on the OIF-CEI-02.0 standard. To speed backplane communication receiver has been decounteract the serious Inter-Syrmbol-Interference （ISI）, the core employed a h...A 6.25 Gbps SerDes core used in the high signed based on the OIF-CEI-02.0 standard. To speed backplane communication receiver has been decounteract the serious Inter-Syrmbol-Interference （ISI）, the core employed a half-rate four-tap decision feedback equalizer （DFE）. The equalizer used the Signsign least mean-squared （SS-LMS） algorithm to realize the coefficient adaptation. An automatic gain control （AGC） amplifier with the sign least mean-squared （S-LMS） algorithm has been used to compensate the transmission media loss. To recover the clock signal from the input data serial and provide for the DFE and AGC, a bang-bang clock recovery （BB-CR） is adopted. A third order phase loop loek （PLL） model was proposed to predict characteristics of the BB-CR. The core has been verified by behavioral modeling in MATLAB. The results indicate that the core can meet the specifications of the backplane receiver. The DFE recovered data over a 34＂ FR-4 backplane has a peak-to-peak jitter of 17 ps, a horizontal eye opening of 0.87 UI, and a vertical eye opening of 500 mVpp.展开更多
This paper presents a lOGb/s highspeed equalizer as the frontend of a receiver for backplane communication. The equalizer combines an analog equalizer and a twotap decisionfeedback equal izer in a halfrate structure t...This paper presents a lOGb/s highspeed equalizer as the frontend of a receiver for backplane communication. The equalizer combines an analog equalizer and a twotap decisionfeedback equal izer in a halfrate structure to reduce the intersymbolinterference （ISI） of the communication chan nel. By employing inductive peaking technique for the highfrequency boost circuit, the bandwidth and the boost of the analog equalizer are improved. The decisionfeedback equalizer optimizes the size of the CMLbased circuit such as D flipflops （DFF） and multiplex （MUX）, shortening the feedback path delay and speeding up the operation considerably. Designed in the 0. 181μm CMOS technology, the equalizer delivers 10Gb/s data over 18in FR4 trace with 28dB loss while drawing 27mW from a 1.8V supply. The overall chip area including pads is 0. 6 -0.7mm2.展开更多
MIMO-DFE(Multiple-Input-Multiple-Output Decision Feedback Equalizer) based receiver architectures are researched recently to detect signals in BLAST(Bell laboratories LAyered Space-Time) over frequency-selective chann...MIMO-DFE(Multiple-Input-Multiple-Output Decision Feedback Equalizer) based receiver architectures are researched recently to detect signals in BLAST(Bell laboratories LAyered Space-Time) over frequency-selective channels. Due to their recursive structure, these receivers may suffer from error propagation which results in an overall mean square error degradation. An MIMO-DFE based BLAST receiver with limited error propagation to combat frequencyselective channel is proposed, which employs both norm constraint on feedback filter taps and soft decision device. Simulation results show that the proposed receiver outperforms conventional ones in various frequency selective channels.展开更多
This paper evaluates the effect of decision feedback equalizer( DFE) error propagation for400 Gb/s Ethernet( 400 GbE) electrical link in order to propose some effective methods to improve bit error rate( BER). First,a...This paper evaluates the effect of decision feedback equalizer( DFE) error propagation for400 Gb/s Ethernet( 400 GbE) electrical link in order to propose some effective methods to improve bit error rate( BER). First,an analytical model for DFE burst error length distribution is proposed and simulated based on a NRZ electrical link in which a 5-tap DFE combined with a multiple-tap feed forward equalizer( FFE) is included. Then,a detailed derivation for BER considering DFE error propagation is given based on the distribution of burst error run length and the BER performance with and without forward error correction( FEC) is simulated too. After that,this paper investigates several MUX-based FEC interleaving methods including their complexity and latency in order to improve BER further. At last,three FEC interleaving schemes are compared not only in interleaving gain,but also in hardware complexities and latencies. Simulation results show that pre-interleave bit muxing can obtain good tradeoff between BER and complexity for 400 Gb E electrical link.展开更多
基金Supported by the High Technology Research and Development Programme of China (No. 2003AA31g030).
文摘A 6.25 Gbps SerDes core used in the high signed based on the OIF-CEI-02.0 standard. To speed backplane communication receiver has been decounteract the serious Inter-Syrmbol-Interference （ISI）, the core employed a half-rate four-tap decision feedback equalizer （DFE）. The equalizer used the Signsign least mean-squared （SS-LMS） algorithm to realize the coefficient adaptation. An automatic gain control （AGC） amplifier with the sign least mean-squared （S-LMS） algorithm has been used to compensate the transmission media loss. To recover the clock signal from the input data serial and provide for the DFE and AGC, a bang-bang clock recovery （BB-CR） is adopted. A third order phase loop loek （PLL） model was proposed to predict characteristics of the BB-CR. The core has been verified by behavioral modeling in MATLAB. The results indicate that the core can meet the specifications of the backplane receiver. The DFE recovered data over a 34＂ FR-4 backplane has a peak-to-peak jitter of 17 ps, a horizontal eye opening of 0.87 UI, and a vertical eye opening of 500 mVpp.
基金Supported by the National High Technology Research and Development Programme of China(No.2011AA10305)
文摘This paper presents a lOGb/s highspeed equalizer as the frontend of a receiver for backplane communication. The equalizer combines an analog equalizer and a twotap decisionfeedback equal izer in a halfrate structure to reduce the intersymbolinterference （ISI） of the communication chan nel. By employing inductive peaking technique for the highfrequency boost circuit, the bandwidth and the boost of the analog equalizer are improved. The decisionfeedback equalizer optimizes the size of the CMLbased circuit such as D flipflops （DFF） and multiplex （MUX）, shortening the feedback path delay and speeding up the operation considerably. Designed in the 0. 181μm CMOS technology, the equalizer delivers 10Gb/s data over 18in FR4 trace with 28dB loss while drawing 27mW from a 1.8V supply. The overall chip area including pads is 0. 6 -0.7mm2.
文摘MIMO-DFE(Multiple-Input-Multiple-Output Decision Feedback Equalizer) based receiver architectures are researched recently to detect signals in BLAST(Bell laboratories LAyered Space-Time) over frequency-selective channels. Due to their recursive structure, these receivers may suffer from error propagation which results in an overall mean square error degradation. An MIMO-DFE based BLAST receiver with limited error propagation to combat frequencyselective channel is proposed, which employs both norm constraint on feedback filter taps and soft decision device. Simulation results show that the proposed receiver outperforms conventional ones in various frequency selective channels.
基金Supported by the National Natural Science Foundation of China(No.61471119)
文摘This paper evaluates the effect of decision feedback equalizer( DFE) error propagation for400 Gb/s Ethernet( 400 GbE) electrical link in order to propose some effective methods to improve bit error rate( BER). First,an analytical model for DFE burst error length distribution is proposed and simulated based on a NRZ electrical link in which a 5-tap DFE combined with a multiple-tap feed forward equalizer( FFE) is included. Then,a detailed derivation for BER considering DFE error propagation is given based on the distribution of burst error run length and the BER performance with and without forward error correction( FEC) is simulated too. After that,this paper investigates several MUX-based FEC interleaving methods including their complexity and latency in order to improve BER further. At last,three FEC interleaving schemes are compared not only in interleaving gain,but also in hardware complexities and latencies. Simulation results show that pre-interleave bit muxing can obtain good tradeoff between BER and complexity for 400 Gb E electrical link.
