Quantized Decoders that Maximize Mutual Information for Polar Codes

In this paper,we innovatively associate the mutual information with the frame error rate(FER)performance and propose novel quantized decoders for polar codes.Based on the optimal quantizer of binary-input discrete memoryless channels(BDMCs),the proposed decoders quantize the virtual subchannels of polar codes to maximize mutual information(MMI)between source bits and quantized symbols.The nested structure of polar codes ensures that the MMI quantization can be implemented stage by stage.Simulation results show that the proposed MMI decoders with 4 quantization bits outperform the existing nonuniform quantized decoders that minimize mean-squared error(MMSE)with 4 quantization bits,and yield even better performance than uniform MMI quantized decoders with 5 quantization bits.Furthermore,the proposed 5-bit quantized MMI decoders approach the floating-point decoders with negligible performance loss.

Unifying Convolution and Transformer Decoder for Textile Fiber Identification

At present,convolutional neural networks(CNNs)and transformers surpass humans in many situations(such as face recognition and object classification),but do not work well in identifying fibers in textile surface images.Hence,this paper proposes an architecture named FiberCT which takes advantages of the feature extraction capability of CNNs and the long-range modeling capability of transformer decoders to adaptively extract multiple types of fiber features.Firstly,the convolution module extracts fiber features from the input textile surface images.Secondly,these features are sent into the transformer decoder module where label embeddings are compared with the features of each type of fibers through multi-head cross-attention and the desired features are pooled adaptively.Finally,an asymmetric loss further purifies the extracted fiber representations.Experiments show that FiberCT can more effectively extract the representations of various types of fibers and improve fiber identification accuracy than state-of-the-art multi-label classification approaches.

Viterbi Decoder ACS单元中路径度量值存储空间的优化

ACS单元的设计及路径度量(PM)值的存储是Viterbi Decoder硬件实现的重要部分之一。介绍了一种码率为1/2的硬判决Viterbi Decoder的ACS部分的硬件实现方法。采用了一种全新的设计与存储方式,即原位运算旋转地址的方式,极大地节省了在ACS运算过程中用以存储路径度量值的RAM空间,大量的实验证明,设计的译码器在资源消耗上有较大优势。

Low-loss belief propagation decoder with Tanner graph in quantum error-correction codes

Quantum error-correction codes are immeasurable resources for quantum computing and quantum communication.However,the existing decoders are generally incapable of checking node duplication of belief propagation(BP)on quantum low-density parity check(QLDPC)codes.Based on the probability theory in the machine learning,mathematical statistics and topological structure,a GF(4)(the Galois field is abbreviated as GF)augmented model BP decoder with Tanner graph is designed.The problem of repeated check nodes can be solved by this decoder.In simulation,when the random perturbation strength p=0.0115-0.0116 and number of attempts N=60-70,the highest decoding efficiency of the augmented model BP decoder is obtained,and the low-loss frame error rate(FER)decreases to 7.1975×10^(-5).Hence,we design a novel augmented model decoder to compare the relationship between GF(2)and GF(4)for quantum code[[450,200]]on the depolarization channel.It can be verified that the proposed decoder provides the widely application range,and the decoding performance is better in QLDPC codes.

Determination of quantum toric error correction code threshold using convolutional neural network decoders

Quantum error correction technology is an important solution to solve the noise interference generated during the operation of quantum computers.In order to find the best syndrome of the stabilizer code in quantum error correction,we need to find a fast and close to the optimal threshold decoder.In this work,we build a convolutional neural network(CNN)decoder to correct errors in the toric code based on the system research of machine learning.We analyze and optimize various conditions that affect CNN,and use the RestNet network architecture to reduce the running time.It is shortened by 30%-40%,and we finally design an optimized algorithm for CNN decoder.In this way,the threshold accuracy of the neural network decoder is made to reach 10.8%,which is closer to the optimal threshold of about 11%.The previous threshold of 8.9%-10.3%has been slightly improved,and there is no need to verify the basic noise.

Efficient VLSI architecture of CAVLC decoder with power optimized

This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code （CAVLC） decoder with power optimized for the H.264/advanced video coding （AVC） standard. In the proposed design, according to the regularity of the codewords, the first one detector is used to solve the low efficiency and high power dissipation problem within the traditional method of table-searching. Considering the relevance of the data used in the process of runbefore＇s decoding, arithmetic operation is combined with finite state machine （FSM）, which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in the module level and the register level respectively, which reduces 43% of the overall dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at the clock constraint of 100 MHz, the synthesis result shows that the design costs 11 300 gates under a 0.25 μm CMOS technology, which meets the demand of real time decoding in the H.264/AVC standard.

Low-complexity MP3 decoder based on Broadcom embedded platform

A low complexity MP3 decoder based on Broadcom embedded platform was proposed. C code level optimization algorithms on inverse quantization, stereo decoding and alias reduction based on PC were proposed to further reduce the amount of memory usage and the computational complex ity. Furthermore, the executable file of the optimized MP3 decoder was generated under the Linux environment, and transplanted to the set top box based on Broadcom embedded platform. Experi ment results showed that the total time for decoding was reduced on the embedded platform, and the goal of real time and fluent playing of audio files was fulfilled, which demonstrated the effectiveness of the proposed MP3 decoder. The proposed MP3 decoder could be applied in fields such xs the set top box based on Broadcom embedded platform and other portable devices.

High Speed Versatile Reed-Solomon Decoder for Correcting Errors and Erasures

A new Chien search method for shortened Reed-Solomon （RS） code is proposed, based on this, a versatile RS decoder for correcting both errors and erasures is designed. Compared with the traditional RS decoder, the weighted coefficient of the Chien search method is calculated sequentially through the three pipelined stages of the decoder. And therefore, the computation of the errata locator polynomial and errata evaluator polynomial needs to be modified. The versatile RS decoder with minimum distance 21 has been synthesized in the Xilinx Virtex-Ⅱ series field programmable gate array （FPGA） xe2v1000-5 and is used by coneatenated coding system for satellite communication. Results show that the maximum data processing rate can be up to 1.3 Gbit/s.

Program Error Mitigation in MLC NAND Flash Memory with Soft Decision Decoders

Benefiting from strong decoding capabilities,soft-decision decoding has been used to replace hard-decision decoding in various communication systems,and NAND flash memory systems are no exception.However,soft-decision decoding relies heavily on accurate soft information.Owing to the incremental step pulse programming(ISPP),program errors(PEs)in multi-level cell(MLC)NAND flash memory have different characteristics compared to other types of errors,which is very difficult to obtain such accurate soft information.Therefore,the characteristics of the log-likelihood ratio(LLR)of PEs are investigated first in this paper.Accordingly,a PE-aware statistical method is proposed to determine the usage of PE mitigation schemes.In order to reduce the PE estimating workload of the controller,an adaptive blind clipping(ABC)scheme is proposed subsequently to approximate the PEs contaminated LLR with different decoding trials.Finally,simulation results demonstrate that(1)the proposed PE-aware statistical method is effective in practice,and(2)ABC scheme is able to provide satisfactory bit error rate(BER)and frame error rate(FER)performance in a penalty of negligible increasing of decoding latency.

Elimination of the Background Noise of the Decoded Image in Fresnel Zone Plate Scanning Holography

A method of digitally high pass filtering in frequency domain is proposed to eliminate the background noise of the decoded image in Fresnel zone plate scanning holography. The high pass filter is designed as a circular stop, which should be suitable to suppressing the background noise significantly and remain much low frequency information of the object. The principle of high pass filtering is that the Fourier transform of the decoded image is multiplied with the high pass filter. Thus the frequency spectrum of the decoded image without the background noise is achieved. By inverse Fourier transform of the spectrum of the decoded image after multiplying operation, the decoded image without the background noise is obtained. Both of the computer simulations and the experimental results show that the contrast and the signal-to-noise ratio of the decoded image are significantly improved with digital filtering.

The Formal Specifications for Protocols of Decoders

This paper presents a formal approach, FSPD (Formal Specifications for Protocols of Decoders), to specify decoder communication protocols. Based on axiomatic, FSPD is a precise language with which programmers could use only one suitable driver to handle various types of decoders. FSPD is helpful for programmers to get high adaptability and reusability of decoder-driver software. Key words formalization - digital video security system - protocol of decoders CLC number TP 311 Biography: YUAN Meng-ting(1976-), Ph.D candidate, research direction: software engineering, formal method.

Implementation of low-density parity-check codes decoder for CCSDS standard

The complexity/performance balanced decoder for low-density parity-check （LDPC） codes is preferred in practical wireless communication systems. A low complexity LDPC decoder for the Consultative Committee for Space Data Systems （CCSDS） standard is achieved in DSP. An ap- proximate decoding algorithm, normalized rain-sum algorithm, is used in the implementation for its low amounts of computation. To reduce the performance loss caused by the approximation, the pa- rameters of the normalized min-sum algorithm are determined by calculating and finding the mini- mum value of thresholds through density evolution. The minimum value which indicates the best per- formance of the decoding algorithm is corresponding with the optimized parameters. In implementa- tion, the memory cost is saved by decomposing the parity-check matrix into submatrices to store and the computation of passing message in decoding is accelerated by using the intrinsic function of DSP. The performance of the decoder with optimized factors is simulated and compared with the ideal BP decoder. The result shows they have about the same performance.

Radiation Tolerant Viterbi Decoders for On-Board Processing(OBP) in Satellite Communications

Modern satellite communication systems require on-board processing(OBP)for performance improvements,and SRAM-FPGAs are an attractive option for OBP implementation.However,SRAM-FPGAs are sensitive to radiation effects,among which single event upsets(SEUs)are important as they can lead to data corruption and system failure.This paper studies the fault tolerance capability of a SRAM-FPGA implemented Viterbi decoder to SEUs on the user memory.Analysis and fault injection experiments are conducted to verify that over 97%of the SEUs on user memory would not lead to output errors.To achieve a better reliability,selective protection schemes are then proposed to further improve the reliability of the decoder to SEUs on user memory with very small overhead.Although the results are obtained for a specific FPGA implementation,the developed reliability estimation model and the general conclusions still hold for other implementations.

Design and Implementation of the Motion Compensation Module for HDTV Video Decoder

This paper presented a new solution for motion compensation module in the high definition television (HDTV) video decoder. The overall architecture and the design of the major functional units, such as the motion vector decoder, the predictor, and the mixer, were discussed. Based on the exploitation of the special characteristics inherent in the motion compensation algorithm, the motion compensation module and its functional units adopt various novel architectures in order to allow the module to meet real-time constraints. This solution resolves the problem of high hardware costs, low bus efficiency and complex control schemes in conventional designs.

Comparison and Design of Decoder in B3G Mobile Communication System

Turbo code has been shown to have ability to achieve performance that is close to Shannon limit. It has been adopted by various commercial communication systems. Both universal mobile telecommunications system (UMTS) TDD and FDD have also employed turbo code as the error correction coding scheme. It outperforms convolutional code in large block size, but because of its time delay, it is often only used in the non-real-time service. In this paper, we discuss the encoder and decoder structure of turbo code in B3G mobile communication System. In addition, various decoding techniques, such as the Log-MAP, Max-log-MAP and SOVA algorithm for non-real-time service are deduced and compared. The performance results of decoder and algorithms in different configurations are also shown.

A Highly Compatible Circular-Shifting Network for Partially Parallel QC-LDPC Decoder

The conventional methodology for designing QC-LDPC decoders is applied for fixed configurations used in wireless communication standards, and the supported largest expansion factor Z (the parallelism of the layered decoding) is a fixed number. In this paper, we study the circular-shifting network for decoding LDPC codes with arbitrary Z factor, especially for decoding large Z (Z P) codes, where P is the decoder parallelism. By buffering the P-length slices from the memory, and assembling the shifted slices in a fixed routine, the P-parallelism shift network can process Z-parallelism circular-shifting tasks. The implementation results show that the proposed network for arbitrary sized data shifting consumes only one times of additional resource cost compared to the traditional solution for only maximum P sized data shifting, and achieves significant saving on area and routing complexity.

Serial Genetic Algorithm Decoder for Low Density Parity Check Codes

Genetic algorithms are successfully used for decoding some classes of error correcting codes, and offer very good performances for solving large optimization problems. This article proposes a new decoder based on Serial Genetic Algorithm Decoder (SGAD) for decoding Low Density Parity Check (LDPC) codes. The results show that the proposed algorithm gives large gains over sum-product decoder, which proves its efficiency.

A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazards Filtering

A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have been operated in deep pipelined manner to achieve high transmission rate. The Power dissipation analysis is also investigated and compared with the existing results. The techniques that have been employed in our low-power design are clock-gating and toggle filtering. The synthesized circuits are placed and routed in the standard cell design environment and implemented on a Xilinx XC2VP2fg256-6 FPGA device. Power estimation obtained through gate level simulations indicated that the proposed design reduces the power dissipation of an original Viterbi decoder design by 68.82% and a speed of 145 MHz is achieved.

Service Adaptable 3G Turbo Decoder for Indoor/Low Range Outdoor Environment

For the well-known 3G mobile communications standard UMTS, four different service classes have been specified. Considering two turbo decoding algorithms, like SOVA and log-MAP, it would be desirable to use an efficient turbo decoder. In this paper this decoder is shown to adapt dynamically to different service scenarios, considering parameters like performance and complexity for indoor/low range outdoor operating en-vironment. The scenarios show that for streaming service class real-time class applications the proposed de-coding algorithm depends on data rate;for the majority of scenarios SOVA is proposed, whereas log-MAP is optimal for increased data rates and medium-sized frames. On the other hand, conversational service class real-time applications cannot be established. For the majority of non real-time applications (interactive and background service classes) either algorithm can be used, while log-MAP is proposed for medium data rates and frame lengths.