Functional Verification Based on FPGA for AVS Video Decoder

In this paper,based on the field-programmable gate array(FPGA)xc5vlx220 of Xilinx Company,the FPGA verification method for application specific integrated circuit(ASIC)design is introduced.Firstly,the basic principles of FPGA verification are introduced.Then,the structure of the FPGA board and the verification methods are illustrated.Finally,the workflow of FPGA verification for audio video coding standard(AVS)decoder and the method of restoring images are introduced in detail.The FPGA resources occupancy is shown and analyzed.The result shows that FPGA can verify the ASIC rapidly and effectively so as to shorten the development cycle.

Research and Design of MP3 Player Decoder based on FPGA

The paper takes a method of a low speed processer based on FPGA hardware accelerator SOC units to realize the MP3 player, and include some peripheral devices. The experimental results show that the system has implemented the basic functions of the MP3 player, having its own advantages on increasing the decoding speed and reducing the system consumption. The system is convenient to redesign for more function in the future. In conclusion, it has a wide application prospect.

Implementation of encoder and decoder for LDPC codes based on FPGA

This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.

An FPGA-based LDPC decoder with optimized scale factor of NMS decoding algorithm

Considering that the hardware implementation of the normalized minimum sum(NMS)decoding algorithm for low-density parity-check(LDPC)code is difficult due to the uncertainty of scale factor,an NMS decoding algorithm with variable scale factor is proposed for the near-earth space LDPC codes(8177,7154)in the consultative committee for space data systems(CCSDS)standard.The shift characteristics of field programmable gate array(FPGA)is used to optimize the quantization data of check nodes,and finally the function of LDPC decoder is realized.The simulation and experimental results show that the designed FPGA-based LDPC decoder adopts the scaling factor in the NMS decoding algorithm to improve the decoding performance,simplify the hardware structure,accelerate the convergence speed and improve the error correction ability.

基于DCNv2和Transformer Decoder的隧道衬砌裂缝高效检测模型研究

为解决因衬砌裂缝性状随机、分布密集、标注框分辨率低所导致的现有模型识别精度低、检测速度慢及参数量庞大等问题,以第2版可变形卷积网络(DCNv2)和端到端变换器解码器(Transformer Decoder)为基础对YOLOv8网络框架进行改进,提出了面向衬砌裂缝的检测模型DTD-YOLOv8。首先,通过引入DCNv2对YOLOv8主干卷积网络C2f进行融合以实现模型对裂缝形变特征的准确快速感知,同时采用Transformer Decoder对YOLOv8检测头进行替换以实现端到端框架内完整目标检测流程,从而消除因Anchor-free处理模式所带来的计算消耗。采用自建裂缝数据集对SSD,Faster-RCNN,RT-DETR,YOLOv3,YOLOv5,YOLOv8和DTD-YOLOv8的7种检测模型进行对比验证。结果表明:改进模型F1分数和mAP@50值分别为87.05%和89.58%;其中F1分数相较其他6种模型分别提高了14.16%,7.68%,1.55%,41.36%,8.20%和7.40%;mAP@50分别提高了28.84%,15.47%,1.33%,47.65%,10.14%和10.84%。改进模型参数量仅为RT-DETR的三分之一,检测单张图片的速度为16.01 ms,FPS为65.46帧每秒,对比其他模型检测速度得到提升。该模型在面向运营隧道裂缝检测任务需求时能够表现出高效的性能。

Parallel Implementation of the CCSDS Turbo Decoder on GPU

This paper presents a software turbo decoder on graphics processing units(GPU).Unlike previous works,the proposed decoding architecture for turbo codes mainly focuses on the Consultative Committee for Space Data Systems(CCSDS)standard.However,the information frame lengths of the CCSDS turbo codes are not suitable for flexible sub-frame parallelism design.To mitigate this issue,we propose a padding method that inserts several bits before the information frame header.To obtain low-latency performance and high resource utilization,two-level intra-frame parallelisms and an efficient data structure are considered.The presented Max-Log-Map decoder can be adopted to decode the Long Term Evolution(LTE)turbo codes with only small modifications.The proposed CCSDS turbo decoder at 10 iterations on NVIDIA RTX3070 achieves about 150 Mbps and 50Mbps throughputs for the code rates 1/6 and 1/2,respectively.

Quantized Decoders that Maximize Mutual Information for Polar Codes

In this paper,we innovatively associate the mutual information with the frame error rate(FER)performance and propose novel quantized decoders for polar codes.Based on the optimal quantizer of binary-input discrete memoryless channels(BDMCs),the proposed decoders quantize the virtual subchannels of polar codes to maximize mutual information(MMI)between source bits and quantized symbols.The nested structure of polar codes ensures that the MMI quantization can be implemented stage by stage.Simulation results show that the proposed MMI decoders with 4 quantization bits outperform the existing nonuniform quantized decoders that minimize mean-squared error(MMSE)with 4 quantization bits,and yield even better performance than uniform MMI quantized decoders with 5 quantization bits.Furthermore,the proposed 5-bit quantized MMI decoders approach the floating-point decoders with negligible performance loss.

用于图像边缘检测的SOC FPGA系统

图像处理领域中,往往存在着软件处理实时性较差、FPGA硬件功耗大、片上资源使用较多的问题。为此,论文设计了一种资源消耗少、处理速度快的图像边缘检测系统。在FPGA上实现图像采集、图像灰度化、二值化、形态学滤波、优化的Canny边缘检测算法等功能,由硬核处理器实现外设及其IP核的映射,并配置摄像头、DDR3等设备的驱动程序。通过AXI总线协议实现HPS到FPGA的桥接,完成整个SOC FPGA系统的搭建。图像检测结果表明,该图像处理系统资源消耗低、实时性较高,继承了SOC与FPGA的双重优势,为图像处理方法与应用提供了新的发展方向。

A fringe jump counting method for the phase measurement in the HCN laser interferometer on EAST and its FPGA-based implementation

Electron density in fusion plasma is usually diagnosed using laser-aided interferometers. The phase difference signal obtained after phase demodulation is wrapped, which is also called a fringe jump. A method has been developed to unwrap the phase difference signal in real time using FPGA, specifically designed to handle fringe jumps in the hydrogen cyanide(HCN) laser interferometer on the EAST superconducting tokamak. This method is designed for a phase demodulator using the fast Fourier transform(FFT) method at the front end. The method is better adapted for hardware implementation compared to complex mathematical analysis algorithms, such as field programmable gate array(FPGA). It has been applied to process the phase measurement results of the HCN laser interferometer on EAST in real time. Electron density results show good confidence in the fringe jump unwrapping method. Further possible application in other laser interferometers, such as the POlarimeter-INTerferometer(POINT)system on EAST tokamak is also discussed.

Identification of Important FPGA Modules Based on Complex Network

The globalization of hardware designs and supply chains,as well as the integration of third-party intellectual property(IP)cores,has led to an increased focus from malicious attackers on computing hardware.However,existing defense or detection approaches often require additional circuitry to perform security verification,and are thus constrained by time and resource limitations.Considering the scale of actual engineering tasks and tight project schedules,it is usually difficult to implement designs for all modules in field programmable gate array(FPGA)circuits.Some studies have pointed out that the failure of key modules tends to cause greater damage to the network.Therefore,under limited conditions,priority protection designs need to be made on key modules to improve protection efficiency.We have conducted research on FPGA designs including single FPGA systems and multi-FPGA systems,to identify key modules in FPGA systems.For the single FPGA designs,considering the topological structure,network characteristics,and directionality of FPGA designs,we propose a node importance evaluationmethod based on the technique for order preference by similarity to an ideal solution(TOPSIS)method.Then,for the multi-FPGA designs,considering the influence of nodes in intra-layer and inter-layers,they are constructed into the interdependent network,and we propose a method based on connection strength to identify the important modules.Finally,we conduct empirical research using actual FPGA designs as examples.The results indicate that compared to other traditional indexes,node importance indexes proposed for different designs can better characterize the importance of nodes.

Passive neutron multiplicity device for^(240)Pu measurement based on FPGA

A passive neutron multiplicity measurement device,FH-NCM/S1,based on field-programmable gate arrays(FPGAs),is developed specifically for measuring the mass of plutonium-240(^(240)Pu)in mixed oxide fuel.FH-NCM/S1 adopts an inte-grated approach,combining the shift register analysis mode with the pulse-position timestamp mode using an FPGA.The optimal effective length of the^(3)He neutron detector was determined to be 30 cm,and the thickness of the graphite reflector was ascertained to be 15 cm through MCNP simulations.After fabricating the device,calibration measurements were per-formed using a^(252)Cf neutron source;a detection efficiency of 43.07%and detector die-away time of 55.79μs were observed.Nine samples of plutonium oxide were measured under identical conditions using the FH-NCM/S1 in shift register analysis mode and a plutonium waste multiplicity counter.The obtained double rates underwent corrections for detection efficiency(ε)and double gate fraction(f_(d)),resulting in corrected double rates(D_(c)),which were used to validate the accuracy of the shift register analysis mode.Furthermore,the device exhibited fluctuations in the measurement results,and within a single 20 s measurement,these fluctuations remained below 10%.After 30 cycles,the relative error in the mass of^(240)Pu was less than 5%.Finally,correlation calculations confirmed the robust consistency of both measurement modes.This study holds specific significance for the subsequent design and development of neutron multiplicity devices.

基于 FPGA 的实时边缘检测控制系统研究

本文属于图像识别处理技术领域,提出一种基于FPGA的实时边缘检测控制系统。本文通过FPGA对摄像头进行寄存器配置,采集并得到原始图像,对采集的图像进行数字图像灰度处理,均值滤波、sobel边缘检测计算、二值化处理后并转化为RGB等操作,提取出目标图像的图像边缘轨迹,把图像边缘数据缓存到DDR里面,通过对FPGA内部DDR读写控制模块的处理,把DDR内部图像数据转成RGB格式,并通过HDMI显示器实时显示出目标图像边缘。本文采用改进型的sobel边缘提取算法,能够在边缘提取过程中细化边缘宽度,去除伪边缘,同时滤除多余的图像噪声,使输出的边缘图像更加符合实际的边缘信息。

基于ML-Decoder多分量雷达信号脉内调制识别方法

在现代电子侦察领域,由于电磁环境复杂,脉冲流密度较大,存在同时接收多个雷达信号的情况,多个雷达信号会在时域和频域出现重叠问题,使得雷达信号的特征变得混淆复杂。雷达信号的脉冲调制识别研究在单分量信号中取得了较好的效果,而在多分量雷达信号领域中,需要更多创新方法。为了解决上述问题,提出基于多标签解码器网络(Multi-Lable Decoder Network)框架。该网络框架首先用Choi-Williams分布(Choi-Williams Distribution,CWD)将一维信号转变为时频图。然后通过卷积神经网络提取特征,将提取的特征和查询向量一起送进decoder分类器中。decoder分类器通过标签查询的方法匹配特征信息,有效地避免传统卷积神经网络通过全局池化而淹没丰富的特征。用该方法对由六种典型雷达信号随机组成的多分量雷达信号经行调制识别分析,平均识别准确率达到93.9%,优于所对比的其他深度学习算法。

Machine learning algorithm partially reconfigured on FPGA for an image edge detection system

Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for this process is to combine inertial navigation system sensor information with the global navigation satellite system(GNSS)signal.However,some factors can interfere with the GNSS signal,such as ionospheric scintillation,jamming,or spoofing.One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images.But a high effort is required for image edge extraction.Here a support vector regression(SVR)model is proposed to reduce this computational load and processing time.The dynamic partial reconfiguration(DPR)of part of the SVR datapath is implemented to accelerate the process,reduce the area,and analyze its granularity by increasing the grain size of the reconfigurable region.Results show that the implementation in hardware is 68 times faster than that in software.This architecture with DPR also facilitates the low power consumption of 4 mW,leading to a reduction of 57%than that without DPR.This is also the lowest power consumption in current machine learning hardware implementations.Besides,the circuitry area is 41 times smaller.SVR with Gaussian kernel shows a success rate of 99.18%and minimum square error of 0.0146 for testing with the planning trajectory.This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application,thus contributing to lower power consumption,smaller hardware area,and shorter execution time.

基于encoder-decoder框架的城镇污水厂出水水质预测

由于污水厂的出水水质指标繁多、污水处理过程中反应复杂、时序非线性程度高,基于机理模型的预测方法无法取得理想效果。针对此问题,提出基于深度学习的污水厂出水水质预测方法,并以吉林省某污水厂监测水质为来源数据,利用多种结合encoder-decoder结构的神经网络预测水质。结果显示,所提结构对LSTM和GRU网络预测能力都有一定提升,对长期预测能力提升更加显著,ED-GRU模型效果最佳,短期预测中的4个出水水质指标均方根误差(RMSE)为0.7551、0.2197、0.0734、0.3146,拟合优度(R2)为0.9013、0.9332、0.9167、0.9532,可以预测出水质局部变化,而长期预测中的4个指标RMSE为1.7204、1.7689、0.4478、0.8316,R2为0.4849、0.5507、0.4502、0.7595,可以预测出水质变化趋势,与顺序结构相比,短期预测RMSE降低10%以上,R2增加2%以上,长期预测RMSE降低25%以上,R2增加15%以上。研究结果表明,基于encoder-decoder结构的神经网络可以对污水厂出水水质进行准确预测,为污水处理工艺改进提供技术支撑。

基于时空特征融合的Encoder-Decoder多步4D短期航迹预测

航迹预测在确保空中交通安全、高效运行中扮演着至关重要的角色。所预测的航迹信息是航迹优化、冲突告警等决策工具的输入,而预测准确性取决于模型对航迹序列特征的提取能力。航迹序列数据是具有丰富时空特征的多维时间序列,其中每个变量都呈现出长短期的时间变化模式,并且这些变量之间还存在着相互依赖的空间信息。为了充分提取这种时空特征,本文提出了基于融合时空特征的编码器-解码器(Spatio-Temporal EncoderDecoder,STED)航迹预测模型。在Encoder中使用门控循环单元(Gated Recurrent Unit,GRU)、卷积神经网络(Convolutional Neural Network,CNN)和注意力机制(Attention,AT)构成的双通道网络来分别提取航迹时空特征,Decoder对时空特征进行拼接融合,并利用GRU对融合特征进行学习和递归输出,实现对未来多步航迹信息的预测。利用真实的航迹数据对算法性能进行验证,实验结果表明,所提STED网络模型能够在未来10 min预测范围内进行高精度的短期航迹预测,相比于LSTM、CNN-LSTM和AT-LSTM等数据驱动航迹预测模型具有更高的精度。此外,STED网络模型预测一个航迹点平均耗时为0.002 s,具有良好的实时性。

“校企共筑、 协同育人” FPGA课程思政的探索与实践

以现场可编程逻辑门阵列(field programmable gate array,FPGA)课程为依托,通过分析当前教学实践中所遇到的问题,提出了构建“校企共筑、协同育人”思政教育融入专业课教学的新形式,为新工科理念下实现电子信息类专业课程的教学改革提供了启发.实践表明,该课程思政实施方案有利于推动学生建立知识、能力、情感等因素融合的综合素质,进一步保障了培养卓越电子工程师的育人成效.

FPGA Design and Implementation of a Convolutional Encoder and a Viterbi Decoder Based on 802.11a for OFDM

In this paper, a modified FPGA scheme for the convolutional encoder and Viterbi decoder based on the IEEE 802.11a standards of WLAN is presented in OFDM baseband processing systems. The proposed design supports a generic, robust and configurable Viterbi decoder with constraint length of 7, code rate of 1/2 and decoding depth of 36 symbols. The Viterbi decoder uses full-parallel structure to improve computational speed for the add-compare-select (ACS) modules, adopts optimal data storage mechanism to avoid overflow and employs three distributed RAM blocks to complete cyclic trace-back. It includes the core parts, for example, the state path measure computation, the preservation and transfer of the survivor path and trace-back decoding, etc. Compared to the general Viterbi decoder, this design can effectively decrease the 10% of chip logic elements, reduce 5% of power consumption, and increase the encoder and decoder working performance in the hardware implementation. Lastly, relevant simulation results using Verilog HDL language are verified based on a Xinlinx Virtex-II FPGA by ISE 7.1i. It is shown that the Viterbi decoder is capable of decoding (2, 1, 7) convolutional codes accurately with a throughput of 80 Mbps.

基于LabVIEW FPGA的压电迟滞补偿控制研究

对压电陶瓷驱动器在工作过程中因迟滞非线性效应造成的误差提出了一种迟滞误差补偿控制方法。首先针对迟滞非线性,基于PI模型构建了相应的迟滞模型,并利用其逆模型对压电驱动器的输入电压进行调整;其次针对PI模型的不足之处,结合PID闭环控制进一步对迟滞误差进行补偿。最后基于LabVIEW FPGA模块搭建了压电迟滞补偿控制系统,并进行了单轴正弦振动轨迹控制试验研究。试验结果表明,在复合控制下,压电陶瓷驱动器在100 Hz以内频率下输出位移的最大相对误差在3%以内。

利用Encoder-Decoder框架的深度学习网络实现绕射波分离及成像

利用单纯绕射波场实现地下地质异常体的识别具有坚实的理论基础,对应的实施方法得到了广泛研究,且有效地应用于实际勘探。但现有技术在微小尺度异常体成像方面收效甚微,相关研究多数以射线传播理论为基础,对于影响绕射波分离成像精度的因素分析并不完备。相较于反射波,由于存在不连续构造而产生的绕射波能量微弱并且相互干涉,同时环境干扰使得绕射波进一步湮没。因此,更高精度的波场分离及单独成像是现阶段基于绕射波超高分辨率处理、解释的重点研究方向。为此,首先针对地球物理勘探中地质异常体的准确定位,以携带高分辨率信息的绕射波为研究对象,系统分析在不同尺度、不同物性参数的异常体情况下绕射波的能量大小及形态特征,掌握绕射波与其他类型波叠加的具体形式;然后根据相应特征性质提出基于深度学习技术的绕射波分离成像方法,即利用Encoder-Decoder框架的空洞卷积网络捕获绕射波场特征,从而实现绕射波分离,基于速度连续性原则构建单纯绕射波场的偏移速度模型并完成最终成像。数据测试表明,该方法最终可满足微小地质异常体高精度识别的需求。