Coverage Optimization for Defect-Tolerance Logic Mapping on Nanoelectronic Crossbar Architectures

Emerging nano-devices with the corresponding nano-architectures are expected to supplement or even replace conventional lithography-based CMOS integrated circuits, while, they are also facing the serious challenge of high defect rates. In this paper, a new weighted coverage is defined as one of the most important evaluation criteria of various defecttolerance logic mapping algorithms for nanoelectronic crossbar architectures functional design. This new criterion is proved by experiments that it can calculate the number of crossbar modules required by the given logic function more accurately than the previous one presented by Yellambalase et al. Based on the new criterion, a new effective mapping algorithm based on genetic algorithm （GA） is proposed. Compared with the state-of-the-art greedy mapping algorithm, the proposed algorithm shows pretty good effectiveness and robustness in experiments on testing problems of various scales and defect rates, and superior performances are observed on problems of large scales and high defect rates.

Defect-Tolerant Mapping of CMOL Circuit Targeting Delay Optimization

In view of the significant number of defective nanodevices in the Cmos/nanowire/MOLecular hybrid(CMOL)circuit,defect-tolerant mapping is an essential step to achieve correct logic operations in defective CMOL circuits.However,less effort has been made to improve circuit delay by defect-tolerant strategies.In this paper,the factors affecting the delay of mapped circuits are analyzed,and the path-tree based defect-tolerant mapping method for the delay optimization is proposed.From the logic-domain,the terminology of the path tree is presented,and the logic circuit is first partitioned into multiple path trees.Then,the mapping areas in the physic-domain are pre-planned for(near)critical path trees.During the mapping process,the specific mapping modes and an updating strategy are formulated to map the path trees:inputs are mapped based on input sorting;(near)critical path trees are mapped with priority,while the others are mapped in a hierarchical way.Finally,an improved tabu search algorithm is employed to verify the validity of the proposed defect-tolerant mapping method.Experimental evaluations on the ISCAS benchmarks show that the proposed method can reduce circuit delay by 15.22%.

An Interfacial Dynamic Crosslinking Approach toward Catalyst-free and Mechanically Robust Elastomeric Vitrimer with a Segregated Structure

Elastomeric vitrimers with covalent adaptable networks are promising candidates to overcome the intrinsic drawbacks of conventional covalently-crosslinked elastomers;however, most elastomeric vitrimers show poor mechanical properties and require the addition of exogenous catalysts. Herein, we fabricate a catalyst-free and mechanically robust elastomeric vitrimer by constructing a segregated structure of sodium alginate (SA) in the continuous matrix of epoxidized natural rubber (ENR), and further crosslinking the composite by exchangeable hydroxyl ester bonds at the ENR-SA interfaces. The manufacturing process of the elastomeric vitrimer is facile and environmentally friendly without hazardous solvents or exogenous catalysts, as the abundant hydroxyl groups of the segregated SA phase can act as catalyst to activate the crosslinking reaction and promote the dynamic transesterification reaction. Interestingly, the segregated SA structure bears most of the load owing to its high modulus and small deformability, and thus ruptures preferentially upon deformation, leading to efficient energy dissipation.Moreover, the periodic stiffness fluctuation between rigid segregated SA phase and soft ENR matrix is beneficial to the crack-resisting. As a result,the elastomeric vitrimer manifests exceptional combination of catalyst-free, defect-tolerance, high tensile strength and toughness. In addition,the elastomeric vitrimer also exhibits multi-shape memory behavior which may further broaden its applications.