Low overhead design-for-testability for scan-based delay fault testing

An efficient design-for-testability （DFT） technique is proposed to achieve low overhead for scan-based delay fault testing. Existing techniques for delay test such as skewed-load or broadside make the test generation process complex and produce lower coverage for scan-based designs as compared with non-scan designs, whereas techniques such as enhanced-scan test can make the test easy but need an extra holding latch to add substantial hardware overhead. A new tri-state holding logic is presented to replace the common holding latch in enhanced-scan test to get a substantial low hardware overhead. This scheme can achieve low delay overhead by avoiding the holding latch on the critical timing scan path. What＇s more, this method can also keep the state and signal activity in the combinational circuit from the scan during data scan-in operation to reduce the power dissipation. Experiment results on a set of ISCAS89 benchmarks show the efficiency of the proposed scheme.

Creep properties and a creep equation of delay outburst coal and its adjacent mudstone

The study of the creep properties of coal and its adjacent mudstone is very important for understanding the mechanism of delay outburst coal. The samples of delay outburst coal and its adjacent mudstone collected from Yongshanqiao mine were used to carry out triaxial creep tests. The influence of confining pressure and axial compression on the creep test was analyzed. An accelerated creep model was constructed in parallel with a nonlinear viscous component and plastic component. It is connected with the traditional Burges creep model in series. A creep model which can describe the nonlinear viscoelastic-plastic creep model of rock was established and the corresponding creep equation was derived.According to the results of the creep test, the related parameters of the equation were fitted. The results show that, under the same confining pressure, instantaneous creep strain, creep strain of deceleration phase and constant rate creep of the coal and its adjacent mudstone are increased with an increase in the deviatoric stress. But at the same axial pressure, all of the above decrease with an increase of confining pressure. The duration time of the deceleration creep phase increases with the increase in the deviatoric stress. The theoretical values of the creep equation are in good agreement with the experimental results. It indicates that the creep properties of the delayed outburst coal and its adjacent mudstone can be well described by the creep model established in this paper.

Exploiting Deterministic TPG for Path Delay Testing

Detection of path delay faults requires two-pattern tests. BIST technique provides a low-cost test solution. This paper proposes an approach to designing a cost-effective deterministic test pattern generator (TPG) for path delay testing. Given a set of pre-generated test-pairs with pre-determined fault coverage, a deterministic TPG is synthesized to apply the given test-pair set in a limited test time. To achieve this objective, configurable linear feedback shift register (LFSR) structures are used. Techniques are developed to synthesize such a TPG, which is used to generate an unordered deterministic test-pair set. The resulting TPG is very efficient in terms of hardware size and speed performance. Simulation of academic benchmark circuits has given good results when compared to alternative solutions.

An Analytical Delay Model

Delay considerttion has been a major issue in design and test of high performance digital circuits . The assumption of input signal change occurring only when all internal nodes are stable restricts the increase of clock frequency. It is no longer true for wave pipelining circuits. However, previous logical delay models are based on the assumption. In addition, the stable time of a robust delay test generally depends on the longest sensitizable path delay. Thus , a new delay model is desirable. This paper explores the necessity first. Then, Boolean process to analytically describe the logical and timing behavior of a digital circuit is reviewed . The concept of sensitization is redefined precisely in this paper. Based on the new concept of sensitization, an analytical delay model is introduced . As a result , many untestable delay faults under the logical delay model can be tested if the output waveforms can be sampled at more time points. The longest sensitiaable path length is computed for circuit design and delay test .