FPGA-based high resolution DPWM control circuit

Two improved structures of high resolution digital pulse width modulator(DPWM) control circuit are proposed. Embedded digital clock manager(DCM) blocks and digital programmable delay circuits are employed as the basic resources to construct the field-programmable gate array(FPGA)-based DPWM implementations. Detailed schemes are illustrated and the circuits have been successfully implemented on the Artix-7 FPGA device developed by Xilinx. Experimental results show that when the basic clock operates at the frequency of 200 MHz, the resolutions of the two approaches can reach 625 ps and 500 ps, respectively. Besides,the presented schemes possess other merits including flexible resolution, strong versatility and relatively good stability.

A Novel Design of Mechanical Switch for the High Overload Environment

The internal structure of the inertial measurement unit(IMU)in active state is easily damaged in the high overload environment.So that the IMU is usually required to be powered within the disappearance of the high overload.In this paper,a mechanical switch is designed to enable the IMU based on the analysis of the impact of high overload on the power-supply circuit.In which,parameters of mechanical switch are determined through theoretical calculation and data analysis.The innovation of the proposed structure lies in that the mechanical switch is triggered through the high overload process and could provide a delay signal for the circuit.After all,the proposed switch is tested through mechanical simulation,impact test and practical test.The experimental results show that the designed mechanical switch can effectively and reliably provide the delay for the circuit and guarantee operation of the IMU under high overload.

A novel SOI-DTMOS structure from circuit performance considerations

The performance of a partially depleted silicon-on-insulator （PDSO1） dynamic threshold MOSFET （DT- MOS） is degraded by the large body capacitance and body resistance. Increasing silicon film thickness can reduce the body resistance greatly, but the body capacitance also increases significantly at the same time. To solve this problem, a novel SOl DTMOSFET structure （drain/source-on-local-insulator structure） is proposed. From ISE simulation, the improvement in delay, obtained by optimizing p-n junction depth and silicon film thickness, is very significant. At the same time, we find that the drive current increases significantly as the thickness of the silicon film increases. Furthermore, only one additional mask is needed to form the local SIMOX, and other fabrication processes are fully compatible with conventional CMOS/SOI technology.