Low overhead design-for-testability for scan-based delay fault testing

An efficient design-for-testability （DFT） technique is proposed to achieve low overhead for scan-based delay fault testing. Existing techniques for delay test such as skewed-load or broadside make the test generation process complex and produce lower coverage for scan-based designs as compared with non-scan designs, whereas techniques such as enhanced-scan test can make the test easy but need an extra holding latch to add substantial hardware overhead. A new tri-state holding logic is presented to replace the common holding latch in enhanced-scan test to get a substantial low hardware overhead. This scheme can achieve low delay overhead by avoiding the holding latch on the critical timing scan path. What＇s more, this method can also keep the state and signal activity in the combinational circuit from the scan during data scan-in operation to reduce the power dissipation. Experiment results on a set of ISCAS89 benchmarks show the efficiency of the proposed scheme.

一种数字后端设计DFT的方法分析

阐述可测试性设计(DFT)的特点。分析一种ASIC设计中DFT的方法,包括定义扫描链、定义测试信号、提取扫描链、写入测试协议,使设计人员可以优化最终芯片制造的功耗、面积和时序。

A DFT Method for Single-Control Testability of RTL Data Paths for BIST

This paper presents a new BIST method for RTL data paths based on single-control testability, a new concept of testability. The BIST method adopts hierarchical test. Test pattern generators are placed only on primary inputs and test patterns are propagated to and fed into each module. Test responses are similarly propagated to response analyzers placed only on primary outputs. For the propagation of test patterns and test responses paths existing in the data path are utilized. The DFT method for the single-control testability is also proposed. The advantages of the proposed method are high fault coverage (for single Stuck-at faults), low hardware overhead and capability of at-speed test. Moreover, test patterns generated by test pattern generators can be fed into each module at consecutive system clocks, and thus, the BIST can also detect some faults of other fault models (e.g., transition faults and delay faults) that require consecutive application of test patterns at speed of system clock.

Metric Based Testability Estimation Model for Object Oriented Design: Quality Perspective

The quality factor of class diagram is critical because it has significant influence on overall quality of the product, delivered finally. Testability has been recognized as a key factor to software quality. Estimating testability at design stage is a criterion of crucial significance for software designers to make the design more testable. Taking view of this fact, this paper identifies testability factors namely effectiveness and reusability and establishes the correlation among testability, effectiveness and reusability and justifies the correlation with the help of statistical measures. Moreover study developed metric based testability estimation model and developed model has been validated using experimental test. Subsequently, research integrates the empirical validation of the developed model for high level acceptance. Finally a hypothesis test performs by the two standards to test the significance of correlation.

基于组合DFT方法的ECSP配比设计策略研究

为提高电控固体推进剂(ECSP)配比设计中能量特性参数计算效率以及解决传统配比设计策略未考虑组分含量同步变化的问题,提出了一种基于revDSD-PBEP86-D3(BJ)泛函的组合密度泛函理论(DFT)方法(co-revDSD),将几何优化、振动分析、单点能计算、单点能外推等步骤组合,并结合非迭代三激发电子相关耦合簇(CCSD(T))方法进行了校正,对比了部分有机物生成焓的实验值和co-revDSD方法的计算值;建立了基于评价指数的配比设计策略,基于co-revDSD方法计算了ECSP组分生成焓,绘制了考虑ECSP不同组分含量同步变化时的能量特性参数云图。结果表明,co-revDSD方法可以高效地计算生成焓,部分有机物的实验值和co-revDSD方法的计算值误差在-5%~5%之间;硝酸羟胺(HAN)的生成焓-250.031 kJ·mol^(-1),聚乙烯醇(PVA)的生成焓与重复单元数成正比,比例系数为-219.117;氧化剂/燃料(O/F)比和Al含量的增大在一定范围内均会造成ECSP的能量特性参数的增大,增大Al含量和O/F比可在比冲合适的条件下尽可能降低燃烧温度及燃气平均相对分子质量。

Study of testability measurement method for equipment based on Bayesian network model

To analyze and evaluate the testability design of equipment, a testability analysis method based on Bayesian network inference model is proposed in the paper. The model can adequately apply testability information and many uncertainty information of design and maintenance process, so it can analyze testability by and large from Bayesian inference. The detailed procedure to analyze and evaluate testability for equipments by Bayesian network is given in the paper. Its modeling process is simple, its formulation is visual, and the analysis results are more reliable than others. Examples prove that the analysis method based on Bayesian network inference can be applied to testability analysis and evaluation for complex equipments.

A Mechanism-based 3D-QSAR and DFT Approach for the Prediction of H5N1 Entry Inhibitory Potency of 3-O-β-chacotriosyl Ursolic Acid Derivatives

In this work, 25 3-O-β-chacotriosyl ursolic acid derivatives were employed to achieve the highly reliable and predictive 3 D-QSAR models by Co MFA and Co MSIA methods, respectively. The predictive capabilities of two constructed CoMFA and CoMSIA models were verified by the leave-one-out cross-validation method. The results showed that the cross-validated coefficient（q2） and non-cross-validated coefficient（R2） were 0.559, 0.981 in the CoMFA model and 0.696, 0.978 in the CoM SIA model, respectively, which suggests that these two models are robust and have good exterior predictive capabilities. Furthermore, based on the contour maps information of two models, ten novel inhibitors with higher inhibitory potency were designed, and the quantum chemical calculation of density functional theory（DFT） was performed to investigate the mechanism why the designed molecules have stronger inhibitory activity than the lead compound. The calculations show that the C-50 position of lead compound is a key active site for the enhancement of inhibitory activity, and it should be introduced into the large electron withdrawing group, which would result in generating potent and selective H5 N1 entry inhibitors. We expect that the results in this paper could provide important information to develop new potent H5 N1 entry inhibitors.

Ethernet Controller SoC Design and Its Low-Power DFT Considerations

In this paper, an Ethernet controller SoC solution and its low power design for testability （DFT） for information appliances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit （MCU）, media access control （MAC） circuit and embedded memories such as static random access memory （SRAM）, read only memory （ROM） and flash are all integrated together. In order to achieve high fault coverage, at the same time with low test power, different DFT techniques are adopted for different circuits： the scan circuit that reduces switching activity is implemented for digital logic circuits; BIST-based method is employed for the on-chip SRAM and ROM. According to the fault-modeling of embedded flash, we resort to a March-like method for flash built in self test （BIST）. By all means above, the result shows that the fault coverage may reach 97%, and the SoC chip is implemented successfully by using 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconductor （CMOS） technology, the die area is 4.8×4.6 mm^2. Test results show that the maximum throughput of Ethemet packets may reach 7Mb·s^1.

A Non-scan DFT Method at RTL Based on Fixed-control Testability to Achieve 100%Fault Efficiency

This paper proposes a non-scan design-for-testability method for register-transfer level circuits where a circuit consists of a controller and a data path. It achieves complete fault efficiency with low hardware overhead and at-speed testing.

Theoretical Design of Complex Molecule via Combination of Natural Lawsone and Synthetic Indoline D131 Dyes for Dye Sensitized Solar Cells Application

The dye sensitized solar cells (DSSCs) have been extensively studied due to their low production cost and simple fabrication process. Dye co-sensitization broadens the absorption spectrum of the sensitizer;thus enhances light harvesting efficiency;and contributes to the improvement of the DSSCs overall efficiency. In this study we performed theoretical design of complex molecule (C45H32N2O4) through combination (esterification reaction) of the natural dye lawsone and synthetic metal free indoline dye D131. The excitation energies, vibration spectra, molecular structures, electronic absorption spectra and electron transitions in individual dyes and complex molecule were investigated using density functional theory (DFT) and time dependent density functional theory (TD-DFT) B3LYP5 methods, with 3-21G, 6-31G and 6-31G(d,p) basis sets. The UV-Vis absorption spectra of the individual dyes and their mixture in chloroform solution were measured using spectrophotometer. For the complex formation reaction, enthalpy, entropy and Gibbs free energy were calculated and the results indicated the reaction was endothermic and non-spontaneous. Electron density distribution of the frontier and adjacent molecular orbitals and energy levels alignment were used for analysis of the electronic spectra and mechanism of transitions. The results indicated that the designed complex molecule satisfied the requirements for good photosensitizer of DSSCs.

Testability Models for Object-Oriented Frameworks

Frameworks are time-tested highly reusable architectural skeleton structures. They are designed ‘abstract’ and ‘inco- mplete’ and are designed with predefined points of variability, known as hot spots, to be customized later at the time of framework reuse. Frameworks are reusable entities thus demand stricter and rigorous testing in comparison to one- time use application. The overall cost of framework development may be reduced by designing frameworks with high testability. This paper aims at discussing a few metric models for testability analysis of object-oriented frameworks in an attempt to having quantitative data on testability to be used to plan and monitor framework testing activities so that the framework testing effort and hence the overall framework development effort may be brought down.

An Application of Paraconsistent Annotated Logic for Design Software Testing Strategies

Nowadays, application model systems for decision-making based on non-classical logic such as Paraconsistent Logic are used successfully in the treatment of uncertainties. The method presented in this paper is based on the fundamental concepts of Paraconsistent Annotated Logic with annotation of 2 values (PAL2v). In this study, two algorithms based on PAL2v are presented gradually, to extract the effects of the contradiction in signals of information from a database of uncertain knowledge. The Paraconsistent Extractors Algorithms of Contradiction Effect-Para Extrctr is applied to filters of networks of analyses (PANets) of signal information, where uncertain and contradictory signals may be found. Software test case scenarios are subordinated to an application model of Paraconsistent decision-making, which provides an analysis using Paraconsistent Logic in the treatment of uncertainties for design software testing strategies. This quality-quantity criterion to evaluate the software product quality is based on the characteristics of software testability analysis. The Para consistent reasoning application model system presented in this case study, reveals itself to be more efficient than the traditional methods because it has the potential to offer an appropriate treatment to different originally contradicting source information.

Quantifying Reusability of Object Oriented Design: A Testability Perspective

The quality factor of class diagram is critical because it has a significant influence on overall quality of the product, delivered finally. Testability analysis, when done early in the software creation process, is a criterion of critical importance to software quality. Reusability is an important quality factor to testability. Its early measurement in object oriented software especially at design phase, allows a design to be reapplied to a new problem without much extra effort. This research paper proposes a research framework for quantification process and does an extensive review on reusability of object oriented software. A metrics based model “Reusability Quantification of Object Oriented Design” has been proposed by establishing the relationship among design properties and reusability and justifying the correlation with the help of statistical measures. Also, “Reusability Quantification Model” is empirically validated and contextual significance of the study shows the high correlation for model acceptance. This research paper facilitates to software developers and designer, the inclusion of reusability quantification model to access and quantify software reusability for quality product.

Adding Pseudo-Random Test Sequence Generator in the Test Simulator for DFT Approach

This paper presents modified version of a realistic test tool suitable to Design For Testability （DFT） and Built-ln Self Test （BIST） environments. A comprehensive tool is developed in the form of a test simulator. The simulator is capable of providing a required goal of test for the Circuit Under Test （CUT）. The simulator uses the approach of fault diagnostics with fault grading procedures to provide the optimum tests. The current version of the simulator embeds features of exhaustive and pseudo-random test generation schemes along with the search solutions of cost effective test goals. The simulator provides facilities of realizing all possible pseudo-random sequence generators with all possible combinations of seeds. The tool is developed on a common Personal Computer （PC） platform and hence no special software is required. Thereby, it is a low cost tool hence economical. The tool is very much suitable for determining realistic test sequences for a targeted goal of testing for any CUT. The developed tool incorporates flexible Graphical User Interface （GUI） procedures and can be operated without any special programming skill. The tool is debugged and tested with the results of many bench mark circuits. Further, this developed tool can be utilized for educational purposes for many courses such as fault-tolerant computing, fault diagnosis, digital electronics, and safe-reliable-testable digital logic designs.

Testable Design and BIST Techniques for Systolic Motion Estimators in Transform Domain

Testable design techniques for systolic motion estimators based on M-testability conditions are proposed in this paper. The whole motion estimator can be viewed as a two-dimensional iterative logic array （ILA） of processing elements （PEs） and multiplying elements （MULs）. The functions of each PE and MUL are modified to be bijective to meet the M-testable conditions. The number of test patterns is 2^w, where w denotes the word length of a PE. The proposed testable design techniques are also suitable for built-in self-test implementation. According to experimental results, our approaches can achieve 99.27 % fault coverage. The area overhead is about 9 %. To verify our approaches, an experimental chip is also implemented.

复杂系统测试性设计与故障诊断策略研究进展

测试性设计是提高系统可靠性、安全性、维修性、保障性的重要前沿技术,决定了系统故障检测率和隔离率,直接影响系统的维护(测试)成本。系统测试性设计包含结构化设计、模型化设计、数据驱动设计等多种设计策略。其中,数据驱动设计于近年逐渐兴起并成为重要发展方向之一,该类方法通过对系统测试与故障之间的关系进行建模,依据测试结果进行故障推理,形成故障诊断方案。首先,简要回顾了系统测试性设计的发展历程;其次,重点介绍了测试性设计的研究进展,分析总结了结构化、模型化、数据驱动3类测试方案;然后,介绍了测试性诊断策略构建,根据测试方案中的建模方法确定诊断策略的构建技术,并总结归纳了每类技术的研究特点和适用性;最后,探讨了当前复杂系统测试性设计面临的挑战性问题和可能的未来研究方向。

用于DFT的产品建模方法研究

可检测性是衡量并确保产品功能质量的重要特征参量。运用DFA/M的思想,研究了面向检测的设计（DFT）方法:首先探讨了一般机电产品可检测性的概念,进而提出了广义特征的概念,从而建立有利于产品可检测性评价的产品广义特征模型:并采用基于规则和基于框架的两种知识表示方法分别对可检测性准则、检测工具资源信息进行表达和描述,由此建立支持DFT专家系统的知识库。基于上述思想,在Pro/E平台上开发了DFT专家系统原型,并在产品实例中进行了验证。

基于DFT滤波器组的低时延FPGA语音处理实现研究

提出了WOLA(Weighted Overlap-Add)并行结构的低时延DFT滤波器组的设计和FPGA实现方法.为降低系统总体时延,在综合考虑传递失真、混迭失真的基础上,将群时延引入系统目标函数,并采用非对称综合原型滤波器设计方法,提出迭代算法,实现了DFT滤波器组低时延优化设计.通过对DFT滤波器组中分析和综合功能的关键模块采用多路并行乘法、多级流水加法链设计,实现了并行的WOLA结构DFT滤波器组,降低FPGA实现的计算时延.整个设计在Xilinx公司的Zynq7020型号FPGA芯片上进行实现.PESQ测试表明,设计的DFT滤波器组能取得较好的语音质量.与串行WOLA结构的实现对比表明,在16k Hz语音采样率下,并行的WOLA结构FPGA实现的总时延能降低1.192ms,其中群时延降低12%,计算时延降低29.2%.

基于混合扫描的碳足迹采集终端可测性设计及融合诊断

在“双碳”战略的背景下,针对国内对碳足迹采集终端及系统的迫切需求,提出了基于电力采集终端及通信系统的解决方案,并利用混合边界扫描技术提出了具体的“虚拟探针”可测性设计方案。还针对基于单一类型故障特征进行非线性“簇”电路故障诊断准确率低的难题,在研究小波包变换、PCA及Volterra核特征提取的基础上,提出了小波包变换与PCA特征层融合,并与基于Volterra核特征的初级诊断结果进行决策层融合的故障诊断方法。实验表明,该方法可以有效提高故障诊断的准确率。

基于DFT的含FPGA电路板的测试方法研究

随着微电子技术的不断发展,复杂逻辑器件大量应用到武器装备电路板上,电路板结构功能日趋复杂。与此同时,芯片集成度的大幅提高使得外部可接触的引脚越来越少,这就导致常规的测试方法无法实现对该类电路板的有效测试,电路板维修、检测问题日益突出。因此,在电子设备设计的开始阶段就采用可测性技术。针对含FPGA电路板,对基于DFT的测试方法进行了研究。