The contact pressure acting on the sheet/tools interface has been studied because of growing the concern about the wear of tools. Recent studies make use of numerical simulation software to evaluate and correlate this...The contact pressure acting on the sheet/tools interface has been studied because of growing the concern about the wear of tools. Recent studies make use of numerical simulation software to evaluate and correlate this pressure with the friction and wear generated. Since there are many studies that determine the coefficient of friction in sheet metal forming by bending under tension (BUT) test, the contact pressure between the pin and the sheet was measured using a film that has the ability to record the applied pressure. The vertical force applied to pin was also measured. The results indicate that the vertical force is more accurate to set the contact pressure that using equations predetermined. It was also observed that the contact area between the sheet and the pin is always smaller than the area calculated geometrically. The friction coefficient was determined for the BUT test through several equations proposed by various authors in order to check if there is much variation between the results. It was observed that the friction coefficient showed little variation for each equation, and each one can be used. The material used was the commercially pure aluminum, alloy Al1100.展开更多
In this paper, an Ethernet controller SoC solution and its low power design for testability （DFT） for information appliances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit （MCU）...In this paper, an Ethernet controller SoC solution and its low power design for testability （DFT） for information appliances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit （MCU）, media access control （MAC） circuit and embedded memories such as static random access memory （SRAM）, read only memory （ROM） and flash are all integrated together. In order to achieve high fault coverage, at the same time with low test power, different DFT techniques are adopted for different circuits： the scan circuit that reduces switching activity is implemented for digital logic circuits; BIST-based method is employed for the on-chip SRAM and ROM. According to the fault-modeling of embedded flash, we resort to a March-like method for flash built in self test （BIST）. By all means above, the result shows that the fault coverage may reach 97%, and the SoC chip is implemented successfully by using 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconductor （CMOS） technology, the die area is 4.8×4.6 mm^2. Test results show that the maximum throughput of Ethemet packets may reach 7Mb·s^1.展开更多
文摘The contact pressure acting on the sheet/tools interface has been studied because of growing the concern about the wear of tools. Recent studies make use of numerical simulation software to evaluate and correlate this pressure with the friction and wear generated. Since there are many studies that determine the coefficient of friction in sheet metal forming by bending under tension (BUT) test, the contact pressure between the pin and the sheet was measured using a film that has the ability to record the applied pressure. The vertical force applied to pin was also measured. The results indicate that the vertical force is more accurate to set the contact pressure that using equations predetermined. It was also observed that the contact area between the sheet and the pin is always smaller than the area calculated geometrically. The friction coefficient was determined for the BUT test through several equations proposed by various authors in order to check if there is much variation between the results. It was observed that the friction coefficient showed little variation for each equation, and each one can be used. The material used was the commercially pure aluminum, alloy Al1100.
基金Supported by the National High Technology Research and Development Program of China (2006AA01Z226)
文摘In this paper, an Ethernet controller SoC solution and its low power design for testability （DFT） for information appliances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit （MCU）, media access control （MAC） circuit and embedded memories such as static random access memory （SRAM）, read only memory （ROM） and flash are all integrated together. In order to achieve high fault coverage, at the same time with low test power, different DFT techniques are adopted for different circuits： the scan circuit that reduces switching activity is implemented for digital logic circuits; BIST-based method is employed for the on-chip SRAM and ROM. According to the fault-modeling of embedded flash, we resort to a March-like method for flash built in self test （BIST）. By all means above, the result shows that the fault coverage may reach 97%, and the SoC chip is implemented successfully by using 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconductor （CMOS） technology, the die area is 4.8×4.6 mm^2. Test results show that the maximum throughput of Ethemet packets may reach 7Mb·s^1.
