There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon...There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.展开更多
A scalable readout system （SRS） is designed to provide a general solution for different micro-pattern gas detectors in various applications. The system mainly consists of three kinds of modules： the ASIC card, the ...A scalable readout system （SRS） is designed to provide a general solution for different micro-pattern gas detectors in various applications. The system mainly consists of three kinds of modules： the ASIC card, the adapter card and the front-end card （FEC）. The ASIC cards, mounted with particular ASIC chips, are designed for receiving detector signals. The adapter card is in charge of digitizing the output signals from several ASIC cards. The FEC, edged-mounted with the adapter, has field-programmable gate array （FPGA）-based reconfigurable logic and I/O interfaces, allowing users to choose different ASIC cards and adapters for different experiments, which expands the system to various applications. The FEC transfers data through Gigabit Ethernet protocol realized by a TCP processor （SiTCP） IP core in FPGA. By assembling a flexible number of FECs in parallel through Gigabit Ethernet, the readout system can be tailored to specific sizes to adapt to the experiment scales and readout requirements. In this paper, two kinds of multi-channel ASIC chip, VA140 and AGET, are applied to verify the scalability of this SRS architecture. Based on this VA140 or AGET SRS, one FEC covers 8 ASIC （VA140） cards handling 512 detector channels, or 4 ASIC （AGET） cards handling 256 detector channels, respectively. More FECs can be assembled in crates to handle thousands of detector channels.展开更多
研制了一种适用于高能物理中探测器读出系统的LVDS芯片,采用极低的电压摆幅实现高速差动传输数据,可以实现点对点或一点对多点的连接和传输。芯片包括驱动和接收两部分,均采用0.35um/3.3 V CMOS工艺设计,测试结果显示芯片基本达到预期...研制了一种适用于高能物理中探测器读出系统的LVDS芯片,采用极低的电压摆幅实现高速差动传输数据,可以实现点对点或一点对多点的连接和传输。芯片包括驱动和接收两部分,均采用0.35um/3.3 V CMOS工艺设计,测试结果显示芯片基本达到预期研制目标。展开更多
In this paper,we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit（ASIC） dedicated to CdZnTe detectors for a hard X-ray imager in spa...In this paper,we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit（ASIC） dedicated to CdZnTe detectors for a hard X-ray imager in space applications.The readout channel is comprised of a charge sensitive amplifier,a CR-RC shaping amplifier,an analog output buffer,a fast shaper,and a discriminator.An 8-channel prototype ASIC is designed and fabricated in TSMC 0.35-μm mixed-signal CMOS technology,the die size of the prototype chip is 2.2×2.2 mm^2.The input energy range is from 5 to 350 keV.For this 8-channel prototype ASIC,the measured electrical characteristics are as follows：the overall gain of the readout channel is 210 V/pC,the linearity error is less than 2%,the crosstalk is less than 0.36%,The equivalent noise charge of a typical channel is 52.9 e^- at zero farad plus 8.2 e^- per picofarad,and the power consumption is less than 2.4 mW/channel.Through the measurement together with a CdZnTe detector,the energy resolution is 5.9%at the 59.5-keV line under the irradiation of the radioactive source ^（241）Am.The radiation effect experiments show that the proposed ASIC can resist the total ionization dose（TID） irradiation of higher than200 krad（Si）.展开更多
A BaF2（Barium Fluoride） detector array is designed to precisely measure the（n, γ） cross section at the CSNS-WNS（white neutron source at China Spallation Neutron Source）. It is a 4π solid angle-shaped detector ...A BaF2（Barium Fluoride） detector array is designed to precisely measure the（n, γ） cross section at the CSNS-WNS（white neutron source at China Spallation Neutron Source）. It is a 4π solid angle-shaped detector array consisting of 92 BaF2 crystal elements. To discriminate signals from the BaF2 detector, a pulse shape discrimination method is used, supported by a waveform digitization technique. There are 92 channels for digitizing. The precision and synchronization of clock distribution restricts the performance of waveform digitizing. In this paper, a clock prototype for the BaF2 readout electronics at CSNS-WNS is introduced. It is based on the PXIe platform and has a twin-stage tree topology. In the first stage, clock is synchronously distributed from the tree root to each PXIe crate through a coaxial cable over a long distance, while in the second stage, the clock is further distributed to each electronic module through a PXIe dedicated differential star bus. With the help of this topology, each tree node can fan out up to 20 clocks with 3U size. Test results show the clock jitter is less than 20 ps, which meets the requirements of the BaF2 readout electronics. Besides, this clock system has the advantages of high density, simplicity, scalability and cost saving, so it can be useful for other clock distribution applications.展开更多
Background High-voltage CMOS is a promising technology for the pixel sensor of tracking detectors in the collider experiments.Extensive studies are being carried out by theATLASCollaboration to investigate the possibi...Background High-voltage CMOS is a promising technology for the pixel sensor of tracking detectors in the collider experiments.Extensive studies are being carried out by theATLASCollaboration to investigate the possibility of using theHV-CMOS technology in the HL-LHC upgrade of the ATLAS inner tracker detector.Purpose The CaRIBOu(Control and Readout Itk BOards)is a modular test system developed to test the HV-CMOS pixel sensor prototypes and demonstrators.Methods This test system consists of pixel sensor specific front-end chip boards,a control and readout board(CaR board),a central interface board and the back-end DAQ system.Currently,two DAQ solutions are available for the CaRIBOu system,one is based on the FELIX(front-end link eXchange)readout system and the other is based on the Gigabit Ethernet link.Results Various testbeam experiments have been carried out with the CaRIBOu system since 2015 for the pixel sensors fabricated by the AMS HV-CMOS 180 nm and 350 nm technologies.Conclusion The test results show that this test system is very flexible and could be adapted to the test of different pixel sensors with minimum effort,and the performance meets the testbeam requirements.展开更多
基金supported in part by the National Natural Science Foundation of China(Nos.12005245,12075100,and 11775244)by the Scientific and Technological Innovation Project(No.2020000165)from the Institute of High Energy Physics,Chinese Academy of Sciences+1 种基金partially funded by the Scientific Instrument Development Project of the Chinese Academy of Sciences(No.ZDKYYQ20200007)Youth Innovation Promotion Association of the Chinese Academy of Sciences(No.Y201905).
文摘There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.
基金Supported by National Natural Science Foundation of China(11222552)
文摘A scalable readout system （SRS） is designed to provide a general solution for different micro-pattern gas detectors in various applications. The system mainly consists of three kinds of modules： the ASIC card, the adapter card and the front-end card （FEC）. The ASIC cards, mounted with particular ASIC chips, are designed for receiving detector signals. The adapter card is in charge of digitizing the output signals from several ASIC cards. The FEC, edged-mounted with the adapter, has field-programmable gate array （FPGA）-based reconfigurable logic and I/O interfaces, allowing users to choose different ASIC cards and adapters for different experiments, which expands the system to various applications. The FEC transfers data through Gigabit Ethernet protocol realized by a TCP processor （SiTCP） IP core in FPGA. By assembling a flexible number of FECs in parallel through Gigabit Ethernet, the readout system can be tailored to specific sizes to adapt to the experiment scales and readout requirements. In this paper, two kinds of multi-channel ASIC chip, VA140 and AGET, are applied to verify the scalability of this SRS architecture. Based on this VA140 or AGET SRS, one FEC covers 8 ASIC （VA140） cards handling 512 detector channels, or 4 ASIC （AGET） cards handling 256 detector channels, respectively. More FECs can be assembled in crates to handle thousands of detector channels.
基金supported by the National Key Scientific Instrument and Equipment Development Project(No.2011YQ040082)the National Natural Science Foundation of China(Nos.11475136,11575144,61176094)the Shaanxi Natural Science Foundation of China(No.2015JM1016)
文摘In this paper,we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit（ASIC） dedicated to CdZnTe detectors for a hard X-ray imager in space applications.The readout channel is comprised of a charge sensitive amplifier,a CR-RC shaping amplifier,an analog output buffer,a fast shaper,and a discriminator.An 8-channel prototype ASIC is designed and fabricated in TSMC 0.35-μm mixed-signal CMOS technology,the die size of the prototype chip is 2.2×2.2 mm^2.The input energy range is from 5 to 350 keV.For this 8-channel prototype ASIC,the measured electrical characteristics are as follows：the overall gain of the readout channel is 210 V/pC,the linearity error is less than 2%,the crosstalk is less than 0.36%,The equivalent noise charge of a typical channel is 52.9 e^- at zero farad plus 8.2 e^- per picofarad,and the power consumption is less than 2.4 mW/channel.Through the measurement together with a CdZnTe detector,the energy resolution is 5.9%at the 59.5-keV line under the irradiation of the radioactive source ^（241）Am.The radiation effect experiments show that the proposed ASIC can resist the total ionization dose（TID） irradiation of higher than200 krad（Si）.
基金Supported by National Research and Development plan(2016 YFA0401602)NSAF(U1530111)National Natural Science Foundation of China(11005107)
文摘A BaF2（Barium Fluoride） detector array is designed to precisely measure the（n, γ） cross section at the CSNS-WNS（white neutron source at China Spallation Neutron Source）. It is a 4π solid angle-shaped detector array consisting of 92 BaF2 crystal elements. To discriminate signals from the BaF2 detector, a pulse shape discrimination method is used, supported by a waveform digitization technique. There are 92 channels for digitizing. The precision and synchronization of clock distribution restricts the performance of waveform digitizing. In this paper, a clock prototype for the BaF2 readout electronics at CSNS-WNS is introduced. It is based on the PXIe platform and has a twin-stage tree topology. In the first stage, clock is synchronously distributed from the tree root to each PXIe crate through a coaxial cable over a long distance, while in the second stage, the clock is further distributed to each electronic module through a PXIe dedicated differential star bus. With the help of this topology, each tree node can fan out up to 20 clocks with 3U size. Test results show the clock jitter is less than 20 ps, which meets the requirements of the BaF2 readout electronics. Besides, this clock system has the advantages of high density, simplicity, scalability and cost saving, so it can be useful for other clock distribution applications.
文摘Background High-voltage CMOS is a promising technology for the pixel sensor of tracking detectors in the collider experiments.Extensive studies are being carried out by theATLASCollaboration to investigate the possibility of using theHV-CMOS technology in the HL-LHC upgrade of the ATLAS inner tracker detector.Purpose The CaRIBOu(Control and Readout Itk BOards)is a modular test system developed to test the HV-CMOS pixel sensor prototypes and demonstrators.Methods This test system consists of pixel sensor specific front-end chip boards,a control and readout board(CaR board),a central interface board and the back-end DAQ system.Currently,two DAQ solutions are available for the CaRIBOu system,one is based on the FELIX(front-end link eXchange)readout system and the other is based on the Gigabit Ethernet link.Results Various testbeam experiments have been carried out with the CaRIBOu system since 2015 for the pixel sensors fabricated by the AMS HV-CMOS 180 nm and 350 nm technologies.Conclusion The test results show that this test system is very flexible and could be adapted to the test of different pixel sensors with minimum effort,and the performance meets the testbeam requirements.
