EXACT ANALYSIS OF SPURIOUS SIGNALS IN DIRECT DIGITAL FREQUENCY SYNTHESIZERS DUE TO AMPLITUDE QUANTIZATION

Amplitude quantization is one of the main sources of spurious noise frequencies in Direct Digital Frequency Synthesizers (DDFSs), which affect their application to many wireless telecommu- nication systems. In this paper, two different kinds of spurious signals due to amplitude quantization in DDFSs are exactly formulated in the time domain and detailedly compared in the frequency do- main, and the effects of the DDFS parameter variations on the spurious performance are thoroughly studied. Then the spectral properties and power levels of the amplitude-quantization spurs in the absence of phase-accumulator truncation are emphatically analyzed by waveform estimation and computer simulation, and several important conclusions are derived which can provide theoretical support for parameter choice and spurious performance evaluation in the application of DDFSs.

基于改进型RBF神经网络的直接数字频率合成器设计

提出了一种基于改进型径向基函数(Radial basis function,RBF)神经网络的高性能直接数字频率合成器,相比于传统的直接数字频率合成器避免了相位截断误差并降低了资源消耗。为了进一步提高RBF神经网络的训练效率及稳定性,提出一种改进型的RBF神经网络训练算法。该算法在粗调阶段,利用K-means++算法快速确定初始激活函数中心,使激活函数中心分布更加合理;在细调阶段则采用L-BFGS-B算法,对粗调阶段得到的最佳中心进行精细调整,进一步降低输出误差。通用FPGA平台的实验结果表明,基于改进型RBF神经网络的直接数字频率合成器当输出时钟频率为1.53 MHz时,无杂散动态范围为85.26 dB,相位噪声为-90.50 dBc/Hz@100 kHz,且无需占用额外ROM资源。

便携式生物电阻抗测量系统的设计与应用

生物电阻抗可用于人体成分测量,具有重要的临床意义与应用价值,现阶段的生物电阻抗测量设备仍存在成本高昂、设备笨重的问题。因此,提出了一种便携式生物电阻抗测量系统,其由控制电路、电流发射电路与阻抗测量电路组成,通过微控制器STC12C5A60S2对直接数字频率合成器AD9833、鉴相器AD8302等微型模块的有效控制,实现对不同频率下人体生物电阻抗的精准稳定测量。研究结果表明,该系统在设计复杂度与实现成本远低于商用人体生物电阻抗仪的前提下,实现了与之类似的测量精确度,有望为生物电阻抗测量装置的小型化、便携化、低成本化发展提供新的思路。

基于FPGA的阵列信号发生方法

使用数字发生的阵列信号,可以快速方便地开展阵列信号处理系统的测试和验证。为此设计了一种基于现场可编程门阵列(FPGA)的阵列信号发生方法,通过小数延时和整数延时相结合的方式,实现点频和线性调频的阵列信号发生。

Low spurious noise frequency synthesis based on a DDS-driven wideband PLL architecture

An S-band frequency synthesizer for a stepped-frequency radar is presented. This frequen- cy synthesizer is based on a direct digital synthesizer （ DDS ） -driven wideband phase-locked loop （PLL） architecture which can achieve low spurious noise and rapid frequency hopping simultaneous- ly. The mechanism of introducing high level spurs by the images of DDS digital to analog convertor （DAC） output is analyzed. A novel DDS frequency planning method is proposed to ensure low col- ored noise within the entire bandwidth. The designed output frequency range is 3. 765 -4. 085 GHz, and the step size is 5 MHz with frequency agility of less than 1 μs. Measured results demonstrate that the average spurious free dynamic range （SFDR） is about 64 dBc in a 320 MHz bandwidth.

Measurement of soil electrical conductivity based on direct digital synthesizer(DDS)and digital oscilloscope

A soil electrical conductivity(EC)measurement system based on direct digital synthesizer(DDS)and digital oscilloscope was developed.The system took the“current-voltage four-electrode method”as the design principal and adopted a six-pin structure of the probe,two center pins to measure the soil EC in shallow layer,two outside pins to measure the soil EC in deep layer,and two middle pins for inputting the driving current.A signal generating circuit using DDS technology was adopted to generate sine signals,which was connected with the two middle pins.A digital oscilloscope was used to record and store the two soil output signals with noises in microseconds,which were from the two center pins and two outside pins,respectively.Then a digital bandpass filter was used to filter the soil output signals recorded by the digital oscilloscope.Compared with the traditional analog filter circuit,the digital filter could filter out the noises of all frequency except for the frequency of the excitation source.It could improve the effect of filtering and the accuracy of the soil EC measurement system.The DDS circuit could provide more stable sine signals with larger amplitudes.The use of digital oscilloscope enables us to analyze the soil output signals in microseconds and measure the soil EC more accurately.The new soil EC measurement system based on DDS and digital oscilloscope can provide a new effective tool for soil sensing in precision agriculture.

A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC

This paper presents a high speed ROM-less direct digital frequency synthesizer （DDFS） which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic （CML） is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm^2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0℃.

A high-performance MUX-direct digital frequency synthesizer with quarter ROMs

This paper presents a detailed description of a high-performance direct digital frequency synthesizer （DDFS） using optimized quarter ROMs. To improve the working frequency and spectral purity, an original quarter ROMs structure in 0.13 μm CMOS is brought forward and implemented. The working frequency is increased by 40% compared with Yuan Ling＇s methodIll of implementing a segmented DAC based DDFS. It has been implemented in 0.13 μm CMOS technology. The DDFS has a resolution of 10 bits with a measured SFDR 54 dBc. Its maximum operating frequency is 1.2 GHz by using six pipelining stages. Analytical investigation of improving spectral performances by using dual-slope approximation and pipeline is also presented.

A high speed direct digital frequency synthesizer based on multi-channel structure

This paper presents a direct digital frequency synthesizer （DDFS） for high speed application based on multi-channel structure. This DDFS has phase resolution of 32 bits and magnitude resolution of 12 bits. In order to ensure the high speed and high resolution at the same time, the multi-channel sampling technique is used and a 12 bits linear digital-to-analog converter is implemented. The chip is fabricated in TSMC 130 nm CMOS technology with active area of 0.89 x 0.98 mm2 and total power consumption of 300 mW at a single 1.2 V supply voltage. The maximum operating speed is up to 2.0 GHz at room temperature.

Audio Video Compression Stream Synthesis and Implementation

Multiplex of digital streams is one of the key technologies in audio-video communication, and determines audio-video quality. A design scheme for an MPEG2 compliant digital television system including audio-video encoding and multiplexing was implemented. The principles and elements of system layer stream synthesis were analyzed. The key technologies of video and audio PES packetization were discussed, such as stream structure, scheduling matching, audio-video synchronization, data flow and buffering. DSP and FPGA are combined to construct header information and packet structure. The substitution of traditional RAM or PLD results in high operational efficiency and saves memory space. A scheduling algorithm was introduced for PES coding, using the monitor information of PES buffers. DTS is generated by multiplexer to guarantee synchronization. The system is not only simple but also stable, and maintains synchronization constraints of the standard. It supports both analogy and digital audio-video source input, and provides real-time MPEG2 compliant TS/PS output. It has perfect performance and meets the national broadcasting requirements.

A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications

A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications is successfully realized by the 130 nm CMOS process. A series of novel methods are proposed in this paper.Two band DCOs with high frequency resolution are utilized to cover the frequency band of interest, which is as wide as 2.5 to 5 GHz. An overflow counter is proposed to prevent the ＂pulse-swallowing＂ phenomenon so as to significantly reduce the locking time. A NTW-clamp digital module is also proposed to prevent the overflow of the loop control word. A modified programmable divider is presented to prevent the failure operation at the boundary.The measurement results show that the output frequency range of this frequency synthesizer is 0.8–4.2 GHz. The locking time achieves a reduction of 84% at 2.68 GHz. The best in-band and out-band phase noise performances have reached –100 d Bc/Hz, and –125 d Bc/Hz respectively. The lowest reference spur is –58 d Bc.

基于DPSD算法的交流电磁场检测系统的研制

文中以FPGA为核心设计基于DPSD算法的ACFM检测系统,实现对检测信号自适应滤波,提取幅值的功能。系统由探头、前端处理电路、FPGA、上位机软件组成,并基于FPGA设计DDS激励源。以不锈钢板为测试对象设计试验,验证系统性能。结果表明:系统针对微小裂纹具有良好的检出效果,且在系统稳定性、集成性及灵活性方面具有很好性能。

一种小体积X波段频率合成器设计

介绍了一种小体积频率合成器的设计,该频率合成器通过直接数字频率合成器(DDS)产生线性调频信号,通过锁相环产生固定二本振信号,通过锁相环(PLL)与2倍频器产生一本振信号,通过变频部分完成二次混频产生射频激励信号。同时采用现场可编程门阵列(FPGA)完成DDS控制以及与系统通讯,电源控制部分产生各种电源。

一种基于FPGA的可编程数字本振生成方法

近年来,随着相关技术的不断发展,基于现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)的直接数字频率合成技术(Direct Digital Synthesizer,DDS)已成为目前主流的信号合成技术,广泛应用于雷达、通信、国防等领域。然而,受限于FPGA的系统时钟,合成信号的频率范围有限。为了使合成信号获得更大的频率范围和更高的采样频率,提出一种可编程数字本振生成方法,并将该方法应用于频谱分析仪的数字本振频率合成上。实践证明,该方法能够准确产生需要的可变本振信号,且频率范围不受系统时钟频率限制。

多普勒甚高频全向信标(DVOR)系统现状及发展趋势

介绍了全向信标系统的基本组成原理及功能特点,并对DVOR系统技术现状进行分析,重点阐述了DVOR未来发展方向.

移频轨道电路发码装置的研究与设计

为提高移频轨道电路发码装置输出信号的质量及装置的可靠性,设计一种基于直接数字频率合成器(DDS,Direct Digital Synthesizer)芯片的发码装置。该装置由单片机直接控制DDS芯片产生移频信号,经过后级电路放大滤波后,输出到测试环线上,供车载天线接收;单片机提供RS-485通信电路用来接收上位机的控制数据、有机发光二极管(OLED,Organic Light-Emitting Diode)显示屏和按键,作为便携式设备的人员操作接口。通过测试验证,该装置可精确输出ZPW-2000和FTGS这2种移频轨道电路的移频键控(FSK,Frequency-Shift Keying)调制信号,提高了输出信号的分辨率和精度,从而减小相邻轨道区段间的干扰,便于机车信号设备的解调。与既有的移频轨道电路发码装置相比,该装置具有信号质量高、结构简单、可靠性高、方便操作的优点。

多通道超声相控阵驱动控制系统设计

低强度经颅聚焦超声是一种利用脉冲聚焦超声调控脑神经元的治疗技术。为抑制人颅骨的非均质性和个体结构差异影响,须对多阵元相控阵聚焦换能器的各阵元进行参数调控实现经颅精准定位聚焦,各阵元参数调控需通过相位控制和驱动电路系统来实现。该文设计并搭建了一种基于直接数字式频率合成技术的多通道相位、幅值独立可调的相控驱动系统。实测结果表明,可实现正弦波和方波高精度相控输出,输出信号电压峰峰值在0-37.5 V可调,相位分辨率为0.1°,延时误差小于1 ns,可满足多阵元相控阵聚焦换能器驱动及其所需相位分辨率的需要。

基于FPGA和LabWindows的音频DAC测试方案开发与实现

电子设备集成度的提高对于音频集成电路生产和测试等环节的要求越来越高,尤其是音频数模转换器(Digital to Analog Converter,DAC),本质上为数模混合信号电路,采用数模混合信号自动化测试设备(Automatic Test Equipment,ATE)价格昂贵,而采用传统自动测试仪测试覆盖率低、测试时间长,导致这类电路的测试成本较高且测试产能不足。介绍了一种基于现场可编程门阵列(Field Programmable Gate Array,FPGA)和LabWindows的音频DAC电路测试方案,硬件上用FPGA实现音频测试所需的直接数字频率合成(Direct Digital Frequency Synthesizers,DDFS)模块,软件上通过运用LabWindows自带的采样、加窗、快速傅里叶变换(Fast Fourier Transform,FFT)等数字信号处理函数,快速准确地测试各项模拟参数,并在用户界面(User Interface,UI)显示测试值和后台保存测试数据。

一种FPGA控制DDS实现4FSK&FM调制载波的国产化设计

文章主要介绍一种现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)控制数字频率合成器(Direct Digital Synthesizer,DDS)实现四进制移频键控(Quaternary Frequency Shift Keying,4FSK)&频率调制(Frequency Modulation,FM)调制载波的设计方案,给出技术指标参数、硬件组成框图以及信号处理流程,对4FSK的调制信号和FM信号产生的实施方法进行探讨,并对电路框图中的关键器件进行国产化设计选型。

AD9850 DDS芯片信号源的研制

直接数字合成 ( Direct Digital Synthesize,DDS)是一种重要的频率合成技术 ,具有分辨率高 ,频率变换快等优点。阐述了性能价格比较高的 AD985 0直接数字频率合成器芯片的基本原理和性能特点 ,以及用其研制的 0～ 30 MHz信号源。