DESIGN OF DIFFERENTIAL POWER ANALYSIS RESISTANT CRYPTO CHIP BASED ON TIME RANDOMIZATION

Differential Power Analysis (DPA) is an effective attack method to break the crypto chips and it has been considered to be a threat to security of information system. With analyzing the prin-ciple of resisting DPA,an available countermeasure based on randomization is proposed in this paper. Time delay is inserted in the operation process and random number is precharged to the circuit during the delay time,the normal schedule is disturbed and the power is randomized. Following this meth-odology,a general DPA resistance random precharge architecture is proposed and DES algorithm following this architecture is implemented. This countermeasure is testified to be efficient to resist DPA.

Automatic Voltage Control of Differential Power Grids Based on Transfer Learning and Deep Reinforcement Learning

In terms of model-free voltage control methods,when the device or topology of the system changes,the model’s accuracy often decreases,so an adaptive model is needed to coordinate the changes of input.To overcome the defects of a model-free control method,this paper proposes an automatic voltage control(AVC)method for differential power grids based on transfer learning and deep reinforcement learning.First,when constructing the Markov game of AVC,both the magnitude and number of voltage deviations are taken into account in the reward.Then,an AVC method based on constrained multiagent deep reinforcement learning(DRL)is developed.To further improve learning efficiency,domain knowledge is used to reduce action space.Next,distribution adaptation transfer learning is introduced for the AVC transfer circumstance of systems with the same structure but distinct topological relations/parameters,which can perform well without any further training even if the structure changes.Moreover,for the AVC transfer circumstance of various power grids,parameter-based transfer learning is created,which enhances the target system’s training speed and effect.Finally,the method’s efficacy is tested using two IEEE systems and two real-world power grids.

Differential Power Based Selective Phase Tripping for Fault-resilient Microgrid

Modern fault-resilient microgrids(MGs)require the operation of healthy phases during unbalanced short-circuits to improve the system reliability.This study proposes a differential power based selective phase tripping scheme for MGs consisting of synchronous and inverter-interfaced distributed generators(DGs).First,the differential power is computed using the line-end superimposed voltage and current signals.Subsequently,to make the scheme threshold-free,a power coefficient index is derived and used for identifying faulted phases in an MG.The protection scheme is tested on a standard MG operating in either grid-connected or islanding mode,which is simulated using PSCAD/EMTDC.The efficacy of the scheme is also assessed on the OPAL-RT manufactured real-time digital simulation(RTDS)platform.Further,the performance of the proposed protection scheme is compared with a few existing methods.The results show that the selective tripping of faulted phases in MGs can be achieved quickly and securely using the proposed scheme.

Electric power generation technology of natural gas pressure reduction:Insights from black box-gray box hierarchical exergy analysis and evaluation method

Based on the“three box”exergy analysis model,a black box-gray box hierarchical exergy analysis and evaluation method is put forward in this paper,which is applied to evaluate the power generation technology of differential pressure produced by natural gas expansion.By using the exergy analysis theory,the black box-gray box hierarchical exergy analysis models of three differential pressure power generation technologies are established respectively.Firstly,the“black box”analysis models of main energy consuming equipment are established,and then the“gray box”analysis model of the total system is established.Based on the calculation results of exergy analysis indexes,the weak energy consumption equipment in the whole power generation process is accurately located.Taking a gas field in southwest China as an example,the comprehensive energy consumption evaluation of the three power generation technologies is carried out,and the technology with the best energy consumption condition among the three technologies is determined.Finally,the rationalization improvement measures are put forward from improving the air tightness,replacing the deflector and reducing the flow loss.

Secure and efficient elliptic curve cryptography resists side-channel attacks

An embedded cryptosystem needs higher reconfiguration capability and security. After analyzing the newly emerging side-channel attacks on elliptic curve cryptosystem （ECC）, an efficient fractional width-w NAF （FWNAF） algorithm is proposed to secure ECC scalar multiplication from these attacks. This algorithm adopts the fractional window method and probabilistic SPA scheme to reconfigure the pre-computed table, and it allows designers to make a dynamic configuration on pre-computed table. And then, it is enhanced to resist SPA, DPA, RPA and ZPA attacks by using the random masking method. Compared with the WBRIP and EBRIP methods, our proposals has the lowest total computation cost and reduce the shake phenomenon due to sharp fluctuation on computation performance.

Method Based on Time Randomization to Resist Fault Sensitivity Analysis

A fault sensitivity analysis（FSA）-resistance model based on time randomization is proposed.The randomization unit is composed of two parts,namely the configurable register array（R-A）and the decoder（chiefly random number generator,RNG）.In this way,registers chosen can be either valid or invalid depending on the configuration information generated by the decoder.Thus,the fault sensitivity information can be confusing.Meanwhile,based on this model,a defensive scheme is designed to resist both fault sensitivity analysis（FSA）and differential power analysis（DPA）.This scheme is verified with our experiments.

Next generation of power electronic-converter application for energy-conversion and storage units and systems

By a rearrangement of the traditional supply-converter-load system connection,partial-power-processing-based converters can be used to achieve a reduction in size and cost,increase in system efficiency and lower device power rating.The concept is promising for different applications such as photovoltaic arrays,electric vehicles and electrolysis.For photovoltaic applications,it can drive each cell in the array to its maximum power point with a relatively smaller converter;for electric-vehicle applications,both an onboard charger with reduced weight and improved efficiency as well as a fast charger station handling higher power can be considered.By showing different examples of partial-power-processing application for energy-conversion and storage units and systems,this paper discusses key limitations of partial-power-processing and related improvements from different perspectives to show the potential in future power electronic systems.

A novel PV sub-module-level power-balancing topology for maximum power point tracking under partial shading and mismatch conditions

部分遮挡和串联模块(或子模块)的非匹配条件可在整个光伏系统中导致功率曲线非凸且出现多个局部极值和峰值功率下降的现象。通过功率传输,可将各子模块的工作电压拉平;这样的功率收集操作可生成凸功率曲线,提升光伏系统的峰值功率。本文所述拓扑结构受益于开关电容(Switched capacitor,SC)转换器的概念,是一种子模块级功率平衡概念的具体应用。与现有研究成果相比,其创新点包含无遮挡时停止开关操作、串联线路级可拓展性以及减少功率电子元件使用量。功率电子元件使用量的减少是通过两个子模块共享一个SC转换器的方式实现的,这也能带来降低功率器件能量损耗、降低成本和电路体积的优势。本文给出了所述拓扑结构的插入损耗的理论式,并通过PSpice仿真和原型电路的实验评估,证明了损耗理论解的正确性。这也表明,通过使用所述拓扑结构,有可能提取出部分遮挡的光伏线路的几乎所有可用能量,并将其传输至负载端。

Design of power balance SRAM for DPA-resistance

A power balance static random-access memory（SRAM） for resistance to differential power analysis（DPA） is proposed. In the proposed design, the switch power consumption and short-circuit power consumption are balanced by discharging and pre-charging the key nodes of the output circuit and adding an additional shortcircuit current path. Thus, the power consumption is constant in every read cycle. As a result, the DPA-resistant ability of the SRAM is improved. In 65 nm CMOS technology, the power balance SRAM is fully custom designed with a layout area of 5863.6 μm^2.The post-simulation results show that the normalized energy deviation（NED） and normalized standard deviation（NSD） are 0.099% and 0.04%, respectively. Compared to existing power balance circuits, the power balance ability of the proposed SRAM has improved 53%.

A Standard Cell-Based Leakage Power Analysis Attack Countermeasure Using Symmetric Dual-Rail Logic

Leakage power analysis(LPA) attacks aim at finding the secret key of a cryptographic device from measurements of its static(leakage) power. This novel power analysis attacks take advantage of the dependence of the leakage power of complementary metal oxide semiconductor(CMOS) integrated circuits on the data they process. This paper proposes symmetric dual-rail logic(SDRL), a standard cell LPA attack countermeasure that theoretically resists the LPA attacks. The technique combines standard building blocks to make new compound standard cells, which are close to constant leakage power consumption. Experiment results show SDRL is a promising approach to implement an LPA-resistant crypto processor.

Evaluating and Improving Linear Regression Based Profiling:On the Selection of Its Regularization

Side-channel attacks(SCAs)play an important role in the security evaluation of cryptographic devices.As a form of SCAs,profiled differential power analysis(DPA)is among the most powerful and efficient by taking advantage of a profiling phase that learns features from a controlled device.Linear regression(LR)based profiling,a special profiling method proposed by Schindler et al.,could be extended to generic-emulating DPA(differential power analysis)by on-the-fly profiling.The formal extension was proposed by Whitnall et al.named SLR-based method.Later,to improve SLR-based method,Wang et al.introduced a method based on ridge regression.However,the constant format of L-2 penalty still limits the performance of profiling.In this paper,we generalize the ridge-based method and propose a new strategy of using variable regularization.We then analyze from a theoretical point of view why we should not use constant penalty format for all cases.Roughly speaking,our work reveals the underlying mechanism of how different formats affect the profiling process in the context of side channel.Therefore,by selecting a proper regularization,we could push the limits of LR-based profiling.Finally,we conduct simulation-based and practical experiments to confirm our analysis.Specifically,the results of our practical experiments show that the proper formats of regularization are different among real devices.

An AES chip with DPA resistance using hardware-based random order execution

This paper presents an AES（advanced encryption standard） chip that combats differential power analysis （DPA） side-channel attack through hardware-based random order execution.Both decryption and encryption procedures of an AES are implemented on the chip.A fine-grained dataflow architecture is proposed,which dynamically exploits intrinsic byte-level independence in the algorithm.A novel circuit called an HMF（Hold-MatchFetch） unit is proposed for random control,which randomly sets execution orders for concurrent operations.The AES chip was manufactured in SMIC 0.18μm technology.The average energy for encrypting one group of plain texts（128 bits secrete keys） is 19 nJ.The core area is 0.43 mm^2.A sophisticated experimental setup was built to test the DPA resistance.Measurement-based experimental results show that one byte of a secret key cannot be disclosed from our chip under random mode after 64000 power traces were used in the DPA attack.Compared with the corresponding fixed order execution,the hardware based random order execution is improved by at least 21 times the DPA resistance.