Rapid determination of lithium-ion battery degradation: High C-rate LAM and calculated limiting LLI

Herein,incremental capacity-differential voltage (IC-DV) at a high C-rate (HC) is used as a non-invasive diagnostic tool in lithium-ion batteries,which inevitably exhibit capacity fading caused by multiple mechanisms during charge/discharge cycling.Because battery degradation modes are complex,the simple output of capacity fading does not yield any useful data in that respect.Although IC and DV curves obtained under restricted conditions (<0.1C,25℃) were applied in non-invasive analysis for accurate observation of degradation symptoms,a facile,rapid diagnostic approach without intricate,complex calculations is critical in on-board applications.Herein,Li Ni_(0.5)Mn_(0.3)Co_(0.2)O_(2)(NMC532)/graphite pouch cells were cycled at 4 and 6C and the degradation characteristics,i.e.,loss of active materials (LAM) and loss of lithium inventory (LLI),were parameterized using the IC-DV curves.During the incremental current cycling,the initial steep LAM and LLI slopes underwent gradual transitions to gentle states and revealed the gap between low-and high-current measurements.A quantitative comparison of LAM at high and low C-rate showed that a IC;revealed the relative amount of available reaction region limited by cell polarization.However,this did not provide a direct relationship for estimating the LAM at a low C-rate.Conversely,the limiting LLI,which is calculated at a C-rate approaching 0,was obtained by extrapolating the LLI through more than two points measured at high C-rate,and therefore,the LLI at 0.1C was accurately determined using rapid cycling.

A DVCC-Based Mixed-Mode Biquadratic Circuit

This paper introduces a mixed-mode biquadratic circuit employing DVCCs （differential voltage current conveyors） and grounded passive components. The biquadratic circuit can perform mixed-mode operation selecting the input and output terminals. And the circuit enables LP （low-pass）, BP （band-pass）, HP （high-pass）, BS （band-stop） and AP （all-pass） transfer functions by suitably choosing the input terminals. The circuit parameters o30 and Q can be tuned orthogonally through adjusting the passive components. The biquadratic circuit enjoys very low sensitivities with respect to the circuit components. The achievement example is given together with simulation results by PSPICE.

LOW-POWER LVDS I/O INTERFACE FOR ABOVE 2GB/S-PER-PIN OPERATION

Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementation of LVDS Input/Output (I/O) interface circuits in a standard 0.18 μm CMOS technology using thick gate oxide devices (3.3 V), fully compatible with LVDS standard. In the proposed transmitter, a novel Common-Mode FeedBack (CMFB)circuit is utilized to keep the common-mode output voltage stable over Process, supply Voltage and Temperature (PVT) variations. Because there are no area greedy resistors in the CMFB circuitry, the disadvantage of large die area in existing transmitter structures is avoided. To obtain sufficient gain, the receiver consists of three am- plifying stages: a voltage amplifying stage, a transconductance amplifying stage, and a transimpedance amplifying stage. And to exclude inner nodes with high RC time constant, shunt-shunt negative feedback is introduced in the receiver. A novel active inductor shunt peaking structure is used in the receiver to fulfill the stringent requirements of high speed and wide Common-Mode Input Region (CMIR) without voltage gain, power dissipation and silicon area penalty. Simulation results show that data rates of 2 Gbps and 2.5 Gbps are achieved for the transmitter and receiver with power con- sumption of 13.2 mW and 8.3 mW respectively.

A method for improving reliability communication of LVDS

In order to ensure the reliability and accuracy of low voltage differential signaling(LVDS)used in remote test system serial data transmission,a(7,4)linear block code is proposed.At the expense of a certain effective bandwidth,the bit error rate of data transmission is greatly reduced,and the reliability of data transmission is improved by adding monitoring symbols.The driver CLC001 and the adaptive equalizer CLC012 are used as hardwares to compensate the attenuation of the signal in the long line transmission,improve the signal integrity and ensure the reliability of data transmission.Proved by simulation on a shielded twisted pair cable with a total length of 100 m,this system realizes zero bit error transmission of the serial data at the rate of 240 Mbit/s.

Cache Memory Design for Single Bit Architecture with Different Sense Amplifiers

Most modern microprocessors have one or two levels of on-chip caches to make things run faster,but this is not always the case.Most of the time,these caches are made of static random access memory cells.They take up a lot of space on the chip and use a lot of electricity.A lot of the time,low power is more important than several aspects.This is true for phones and tablets.Cache memory design for single bit architecture consists of six transistors static random access memory cell,a circuit of write driver,and sense amplifiers(such as voltage differential sense amplifier,current differential sense amplifier,charge transfer differential sense amplifier,voltage latch sense amplifier,and current latch sense amplifier,all of which are compared on different resistance values in terms of a number of transistors,delay in sensing and consumption of power.The conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34μW of power which shows that power is reduced up to 83%,77.75%reduction in the case of the current differential sense amplifier,39.62%in case of charge transfer differential sense amplifier and 50%in case of voltage latch sense amplifier when compared to existing latch sense amplifier architecture.Furthermore,power reduction techniques are applied over different blocks of cache memory architecture to optimize energy.The single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078μW of power,i.e.,reduce 28%more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.

A 1.0 V differential VCO in 0.13 μm CMOS technology

A differential complementary LC voltage controlled oscillator （VCO） with high Q on-chip inductor is presented. The parallel resonator of the VCO consists of inversion-mode MOS （I-MOS） capacitors and an on-chip inductor. The resonator Q factor is mainly limited by the on-chip inductor. It is optimized by designing a single turn inductor that has a simulated Q factor of about 35 at 6 GHz. The proposed VCO is implemented in the SMIC 0.13μm 1P8M MMRF CMOS process, and the chip area is 1.0 ×0.8 mm2. The free-running frequency is from 5.73 to 6.35 GHz. When oscillating at 6,35 GHz, the current consumption is 2.55 mA from a supply voltage of 1.0 V and the measured phase noise at 1 MHz offset is -120.14 dBc/Hz. The figure of merit of the proposed VCO is -192.13 dBc/Hz.

A 5 GHz CMOS frequency synthesizer with novel phase-switching prescaler and high-Q LC-VCO

A phase-locked loop（PLL） frequency synthesizer with a novel phase-switching prescaler and a high-Q LC voltage controlled oscillator（VCO） is presented.The phase-switching prescaler with a novel modulus control mechanism is much more robust on process variations.The Q factor of the inductor,I-MOS capacitors and varactors in the VCO are optimized.The proposed frequency synthesizer was fabricated by SMIC 0.13μm 1P8M MMRF CMOS technology with a chip area of 1150×2500μm^2.When locking at 5 GHz,the current consumption is 15 mA from a supply voltage of 1.2 V and the measured phase noise at a 1 MHz offset is -122.45 dBc/Hz.

Synthesis for Current-Mode Sallen-Key Filter Using VDTAs

In this work, an original Sallen-Key second-order low-pass filter is first turned into a current-mode one by means of the adjoint network theorem. Two nodal admittance matrices(NAM) of the filter are then educed. Furthermore, these two matrices are expanded through NAM expansion approach, generating one current-mode Sallen-Key filter, which uses two compact voltage differential trans-conductance amplifiers(VDTAs) and two grounded capacitors, implements not only one low-pass transfer function but two band-pass transfer functions, and provides the non-interrelated control between the natural frequency and quality factor. As an example of the synthesized filter, a second-order VDTA filter with fo=1 MHz, Q=1, HLP=-HBP1=HBP2=1 is designed. The used synthesis approach has been confirmed with the help of circuit and computer analysis.