From Digital Analogs Through Recursive Machines to Quantum Computer

The report examines the evolution of computers from digital analogs through non-yon Neumann machines to quantum computers, which are also digital analogs. In the 60 years of digital analogs successfully developed at the Institute of Electromechanics of the USSR in Leningrad. An important stage in the development of non-classical multiprocessor machine performance and reliability has been the development of recursive machines, which was carried out at the Institute of Cybernetics led V.M.Glushkov and the Leningrad Institute of Aviation Instrumentation. The general approach to the synthesis is carried out through linguo- combinatorial modeling with structured uncertainty.

Simulation and Design Optimization of Novel Microelectromechanical Digital-to-Analog Converter

A microelectromechanical Digital to Analog Converter (DAC) based on Weighted Gap (WG) principle is described,which is analogous to the weighed resistor DAC in electronic circuits.To convert the input of binary voltage to the output of analog displacement,the gaps are proposed to be employed as a scale factor.A finite element method is used to simulate the performance of the DAC.To reduce the error,the structure design is optimized and the maximum error of 0 002μm is obtained.

Research on Digital and Analog Electronic Experiment Teaching Course Management based on UltraLab Network Experiment Platform

Digital circuit and analog circuit courses are basic courses for students of science and engineering universities. Among them,the practical courses are of great significance for students to master the knowledge of electronics. In order to make teachers teaching more efficiently and students studying more quickly,how to update the experimental course in teaching reform is the key point. This paper analyzing the present situation of teaching in the digital circuit and analog circuit courses,the teaching questions in universities. On the basis of it,the innovation measures of experimental teaching methods and contents are discussed. Our school tries to introduce the UltraLab network experiment platform,reform and optimize the teaching methods of related courses.And it’ s accelerating the construction and development of emerging engineering education’ s process,reducing effectively the teacher’s time for managing in equipment,improving the students’ ability to use instruments.

Low Complexity Hybrid Wideband Beamforming for Millimeter-Wave Massive MIMO-OFDM Systems

In mmWave massive multiple-input multiple-output(MIMO)communication systems,the extension of low-complexity narrowband precoding schemes to be operated on wideband systems under frequency-selective channels remains an important challenge at the current time.This paper investigates a low complexity wideband hybrid precoding scheme for mmWave massive MIMO multicarrier systems under a single-user,fully-connected hybrid architecture.We show that the radio frequency(RF)precoding/combining vectors can be directly derived from the eigenvectors of the optimal fully-digital covariance matrix over all subcarriers in order to maximize the sum rate of spectral efficiency.We also suggest a new method that iteratively reduces the residual error between the covariance matrix and the sum of products of precoding matrices over all the subcarriers to improve the performance in the case where the number of RF chains is higher than the number of streams.The results of the simulation show that the proposed schemes’complexity is low compared to the present methods,and their performance can almost reach the upper bound achieved by the optimal full-baseband design.

Digital/Analog Simulation Platform for Distributed Power Flow Controller Based on ADPSS and dSPACE

Distributed power flow controller,which is among the most powerful distributed flexible transmission equipments,is still only in the stage of the oretical research and digital simulation.In order to promote the engineering demonstration of a distributed power flow controller,it is urgent to establish a digital/analog simulation platform that supports closed-loop real-time simulation of a distributed power flow controller.In this paper,the electromagnetic transient model of a distributed power flow controller is established on ADPSS(advanced digital power system simulator).The rapid control prototype realized by dSPACE is connected to ADPSS to form a digital/analog simulation platform for a distributed power flow controller.Through a voltage control and power flow control simulation of the test system with a distributed power flow controller,the correctness and effectiveness of the constructed simulation platform are verified,which provides a new way for the verification of the new theory of a distributed power flow controller.

拳击训练模型人的设计

以三星公司的ARM9内核处理器S3C2440为基础,以Linux操作系统为平台设计了拳击训练模型人。分为硬件设计和软件设计两大部分。硬件设计包括模型人结构、用户操作模块、数据采集模块和LED显示屏4个部分。软件设计是在LINUX操作系统环境下采用C语言编程,主要包括10位高精度A/D采集驱动、定时器驱动、语音播报模块和应用程序的编程。通过CFBLSM拉压力传感器采集使用者击打模型人产生的压力变化值,处理器对一系列压力差值计算后可比较精确地得出使用者击打力量大小。语音播报击打效果提高了使用者的积极性,增加了训练趣味性。实验结果证明,拳击训练模型人成本低廉,操作简单,性能稳定。

Time-stretch analog-to-digital conversion with a photonic crystal fiber

All-optical analog-to-digital conversion (ADC) has been extensively researched to break through the inherently limited operating speed of electronic devices. In this paper, we use the photonic crystal fiber (PCF) for time-stretch (TS) analog-to-digital (A/D) conversion system through generating low noise, linear chirp distribution and flat super-continuum (SC). Based on the radio frequency (RF) analog signal modulated to the linearly chirped super-continuum, the large-dispersion photonic crystal fiber is used for time-domain stretching.

Integration and verification case of IP-core based system on chip design

In this paper, the design and verification process of an automobile-engine-fan control system on chip （SoC） are introduced. The SoC system, SHU-MV08, reuses four new intellectual property （IP） cores and the design flow is accomplished with 0.35 btm chartered CMOS technology. Some special functions of IP cores, the detailed integration scheme of four IP cores, and the verification method of the entire SoC are presented. To settle the verification problems brought by analog IP cores, NanoSim based chip-level mixed-signal verification method is introduced. The verification time is greatly reduced and the first tape-out achieves success which proves the validity of our design.

A survey of high-speed high-resolution current steering DACs

Digital to analog converters(DAC)play an important role as a bridge connecting the analog world and the digital world.With the rapid development of wireless communication,wideband digital radar,and other emerging technologies,better performing high-speed high-resolution DACs are required.In those applications,signal bandwidth and high-frequency linearity often limited by data converters are the bottleneck of the system.This article reviews the state-of-the-art technologies of high-speed and high-resolution DACs reported in recent years.Comparisons are made between different architectures,circuit implementations and calibration techniques along with the figure of merit(FoM)results.

Improvement of Injection-Locked VCSELs for Analog and Digital Communication Systems

VCSEL Injection locking is demonstrated to increase laser bandwidth and reduce non-linearity and chirp. All these properties enhance analog and digital modulation performance.

A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit

An analog/digital reconfigurable automatic gain control （AGC） circuit with a novel DC offset cancel- lation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips. What＇s more, a novel DC offset cancellation （DCOC） circuit with an HPCF （high pass cutoff frequency） less than 10 kHz is proposed. The AGC is fabricated by a 0.18μm CMOS process. Under analog control mode, the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz. Under digital control mode, through a 5-bit digital control word, the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB. The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV, while the offset voltage of 40 mV is introduced into the input. The overall power consumption is less than 3.5 mA, and the die area is 800 ×300μm2.

Catalogs of ground motion parameters for earthquake-prone regions in Kazakhstan

The catalogs of ground motion parameters for earthquake-prone regions of Kazakhstan used for modeling seismic effects in seismic hazard assessment and microzonation are presented.

Digital and analog hybrid control in adaptive interference cancellation system

The digital proportion control is introduced to improve the performance of the analog adaptive interference cancellation system （ICS）. For the high frequency parts of the signals after multiplier are not required,the sampling frequency need not satisfy the sampling theorem for high frequency. Because the sampling,calculation and output expend time in digital control,the ideal condition,delay condition and delay-wait condition are taken into account. Through analyzing the system model with three conditions,we gain the stable conditions of the system,the optimization step factors that can make the system converge fastest and the formulas of the interference cancellation ratios （ICRs）. One step convergence can be accomplished under ideal condition,whereas the system can not converge in one step under delay condition and delay-wait condition. The calculation results show the convergence speed of delay-wait condition is slower than that of delay condition. The ICR is improved with the increase of the step factor which is in stable bound,but the convergence speed is decreased if the step factor exceeds the optimization step factor. In order to avoid that confine,the method of amending the steady state weight to improve the ICR is proposed. The analyses are in agreement with the computer simulations.

An optimized analog to digital converter for WLAN analog front end

A 10 bit 80 MSPS analog to digital converter optimized for WLAN analog front end is presented. In contrast to conventional 1.5 bit pipeline architecture, four optimized multiit multiply digital to analog converter stages are implemented. An on-chip low-noise reference buffer is proposed for SoC integration purposes, and a wide-bandwidth wide swing sample and hold amplifier is also presented for achieving a good dynamic range. The converter was fabricated in 0.18 #m 1P6M CMOS technology, and the core area occupies approximately 0.85 mm2. Measured results show that with an 11 MHz input signal, it provides a 9.4 bit effective number of bits and a 72 dBc spurious frequency dynamic range when sampled at 80 MHz.

An Energy-Efficient 12b 2.56 MS/s SAR ADC Using Successive Scaling of Reference Voltages

This paper presents an energy efficient architecture for successive approximation register(SAR)analog to digital converter(ADC).SAR ADCs with a capacitor array structure have been widely used because of its simple architecture and relatively high speed.However,conventional SAR ADCs consume relatively high energy due to the large number of capacitors used in the capacitor array and their sizes scaled up along with the number of bits.The proposed architecture reduces the energy consumption as well as the capacitor size by employing a new array architecture that scales down the reference voltages instead of scaling up the capacitor sizes.The proposed 12-bit SAR ADC is implemented in Complementary Metal Oxide Semiconductor(CMOS)0.13 um library using Cadence Virtuoso design tool.Simulation results and mathematical model demonstrate the overall energy savings of up to 97.3%compared with conventional SAR ADC,67%compared with the SAR ADC with split capacitor,and 35%compared with the resistor and capacitor(R&C)Hybrid SAR ADC.The ADC achieves an effective number of bits(ENOB)of 11.27 bits and consumes 61.7 uW at sampling rate of 2.56 MS/s,offering an energy consumption of 9.8 fJ per conversion step.The proposed SAR ADC offers 95.5%reduction in chip core area compared to conventional architecture,while occupying an active area of 0.088 mm2.

Design and implementation of the optical fiber control and transmission module in multi-channel broadband digital receiver

An optical fiber control and transmission module is designed and realized based on Virtex-7 field programmable gata array(FPGA), which can be applied in multi-channel broadband digital receivers. The module consists of sampling data transfer submodule and multi-channel synchronous sampling control submodule. The sampling data transmission in 4× fiber link channel is realized with the self-defined transfer protocol. The measured maximum data rate is 4.97 Gbyte/s. By connecting coherent clocks to the transmitter and receiver endpoints and using the self-defined transfer protocol, multi-channel sampling control signals transferred in optical fibers can be received synchronously by each analog-to-digital converter(ADC) with high accuracy and strong anti-interference ability. The module designed in this paper has certain reference value in increasing the transmission bandwidth and the synchronous sampling accuracy of multi-channel broadband digital receivers.

A 14-bit 500-MS/s DAC with digital background calibration

Thelinearityofcurrent-steeringdigital-to-analogconverters（DACs）atlowsignalfrequenciesismainly limited by matching properties of current sources, so large-size current source arrays are widely used for better matching. This, however, results in large gradient errors and parasitic capacitance, which degrade the spurious free dynamic range（SFDR） for high-frequency signals. To overcome this problem, calibration is an effective method.In this paper, a digital background calibration technique for current-steering DACs is presented and verified by a 14-bit DAC in a 0.13 m standard CMOS process. The measured differential nonlinearity（DNL） and integral nonlinearity（INL） are 0.4 LSB and 1.2 LSB, respectively. At 500-MS/s, the SFDR is 70 dB and 50.3 dB for signals of 5.4 MHz and 224 MHz, respectively. The core area is 0.69 mm2and the power consumption is 165 mW from a mixed power supply with 1.2 V and 3.3 V.

A 5-bit time to digital converter using time to voltage conversion and integrating techniques for agricultural products analysis by Raman spectroscopy

Time to digital converter(TDC)is a key block for time-gated single photon avalanche diode(SPAD)arrays for Raman spectroscopy that applicable in the agricultural products and food analysis.In this paper a new dual slope time to digital converter that employs the time to voltage conversion and integrating techniques for digitizing the time interval input signals is presented.The reference clock frequency of the TDC is 100 MHz and the input range is theoretically unlimited.The proposed converter features high accuracy,very small average error and high linear range.Also this converter has some advantages such as low circuit complexity,low power consumption and low sensitive to the temperature,power supply and process changes(PVT)compared with the time to digital converters that used preceding conversion techniques.The proposed converter uses an indirect time to digital conversion method.Therefore,our converter has the appropriate linearity without extra elements.In order to evaluate the proposed idea,an integrating time to digital converter is designed in 0.18 lm CMOS technology and was simulated by Hspice.Comparison of the theoretical and simulation results confirms the proposed TDC operation;therefore,the proposed converter is very convenient for applications which have average speed and low variations in the signal amplitude such as biomedical signals.

A 12-bit 80 MS/s 2 mW SAR ADC with Deliberated Digital Calibration and Redundancy Schemes for Medical Imaging

In this article,we presented a 12-bit 80 MS/s low power successive approximation register(SAR)analog to digital converter(ADC)design.A simplified but effective digital calibration scheme was exploited to make the ADC achieve high resolution without sacrificing more silicon area and power efficiency.A modified redundancy technique was also adopted to guarantee the feasibility of the calibration and meantime ease the burden of the reference buffer circuit.The prototype SAR ADC can work up to a sampling rate of 80 MS/s with the performance of>10.5 bit equivalent number of bits(ENOB),<±1 least significant bit(LSB)differential nonlinearity(DNL)&integrated nonlinearity(INL),while only consuming less than 2 mA current from a 1.1 V power supply.The calculated figure of merit(FoM)is 17.4 fJ/conversion-step.This makes it a practical and competitive choice for the applications where high dynamic range and low power are simultaneously required,such as portable medical imaging.

A platform of digital brain using crowd power

A powerful platform of digital brain is proposed using crowd wisdom for brain research,based on the computational artificial intelligence model of synthesis reasoning and multi-source analogical generating.The design of the platform aims to make it a comprehensive brain database,a brain phantom generator,a brain knowledge base,and an intelligent assistant for research on neurological and psychiatric diseases and brain development.Using big data,crowd wisdom,and high performance computers may significantly enhance the capability of the platform.Preliminary achievements along this track are reported.