This paper presents a low power cyclic analog-to-digital convertor （ADC） design for a wireless monitoring system for orthopedic implants. A two-stage cyclic structure including a single to differential converter, tw...This paper presents a low power cyclic analog-to-digital convertor （ADC） design for a wireless monitoring system for orthopedic implants. A two-stage cyclic structure including a single to differential converter, two multiplying DAC functional blocks （MDACs） and some comparators is adopted, which brings moderate speed and moderate resolution with low power consumption. The MDAC is implemented with the common switched capacitor method. The 1.5-bit stage greatly simplifies the design of the comparator. The operational amplifier is carefully op- timized both in schematic and layout for low power and offset. The prototype chip has been fabricated in a United Microelectronics Corporation （UMC） 0.18-μm 1P6M CMOS process. The core of the ADC occupies only 0.12 mm2. With a 304.7-Hz input and 4-kHz sampling rate, the measured peak SNDR and SFDR are 47.1 dB and 57.8 dBc respectively and its DNL and INL are 0.27 LSB and 0.3 LSB, respectively. The power consumption of the ADC is only 12.5 μW in normal working mode and less than 150 nW in sleep mode.展开更多
基金supported by the National Natural Science Foundation of China(No.60475018)
文摘This paper presents a low power cyclic analog-to-digital convertor （ADC） design for a wireless monitoring system for orthopedic implants. A two-stage cyclic structure including a single to differential converter, two multiplying DAC functional blocks （MDACs） and some comparators is adopted, which brings moderate speed and moderate resolution with low power consumption. The MDAC is implemented with the common switched capacitor method. The 1.5-bit stage greatly simplifies the design of the comparator. The operational amplifier is carefully op- timized both in schematic and layout for low power and offset. The prototype chip has been fabricated in a United Microelectronics Corporation （UMC） 0.18-μm 1P6M CMOS process. The core of the ADC occupies only 0.12 mm2. With a 304.7-Hz input and 4-kHz sampling rate, the measured peak SNDR and SFDR are 47.1 dB and 57.8 dBc respectively and its DNL and INL are 0.27 LSB and 0.3 LSB, respectively. The power consumption of the ADC is only 12.5 μW in normal working mode and less than 150 nW in sleep mode.
