CMOS analog and mixed-signal phase-locked loops: An overview

CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.

Stability Analysis of CPLL with Loop Delay

In this paper,a discrete-time analysis of the third-order charge-pump based phase-locked loops (CPLLs) is presented in the presence of loop delay.The z-domain analysis of the closed-loop transfer function is derived and compared with the traditional s-domain method.The simulation results under SPECTRE show that,due to the sampling nature of CPLL,the traditional s-domain analysis is unable to predict its jitter peaking accurately,especially when the loop delay is taken into consideration.The impact of loop delay on the stability of the third-order CPLL system is further analyzed based on the proposed way.The stability limit of the wide bandwidth CPLL with loop delay is calculated.The circuit simulation results agree well with mathematical analysis.

Application of novel super-exponential iteration algorithm in underwater acoustic channel

A novel variable step-size modified super-exponential iteration(MSEI)decision feedback blind equalization(DFE)algorithm with second-order digital phase-locked loop is put forward to improve the convergence performance of super-exponential iteration DFE algorithm.Based on the MSEI-DFE algorithm,it is first proposed to develop an error function as an improvement to the error function of MSEI,which effectively achieves faster convergence speed of the algorithm.Subsequently,a hyperbolic tangent function variable step-size algorithm is developed considering the high variation rate of the hyperbolic tangent function around zero,so as to further improve the convergence speed of the algorithm.In the end,a second-order digital phase-locked loop is introduced into the decision feedback equalizer to track and compensate for the phase rotation of equalizer input signals.For the multipath underwater acoustic channel with mixed phase and phase rotation,quadrature phase shift keying(QPSK)and 16 quadrature amplitude modulation(16QAM)modulated signals are used in the computer simulation of the algorithm in terms of convergence and carrier recovery performance.The results show that the proposed algorithm can considerably improve convergence speed and steady-state error,make effective compensation for phase rotation,and efficiently facilitate carrier recovery.

An area-saving dual-path loop filter for low-voltage integrated phase-locked loops

This paper proposes an area-saving dual-path loop filter（LPF）for low-voltage integrated phase-locked loops（PLLs）.With this LPF,output current of the lowpass-path charge-pump（CP）is B times（B〉1）as great as that of the integration-path CP.By adding voltages across these two paths,the zero-capacitance is magnified B times equivalently.As a result,the chip size is greatly reduced.Based on this LPF,a 1.2 V 3.5 GHz-band PLL is fabricated in SMIC 0.18μm RFCMOS technology.Its zero-capacitance is only 1/30 of that in conventional second-order LPFs. Measured data show that,at a frequency of 3.20 GHz,phase noise is–120.2 dBc/Hz at 1 MHz offset,reference spur is–72 dBc,and power is 24 mW.

水声信道均衡算法比较研究

简述了自适应均衡算法和盲均衡算法在水声通信中的应用现状,以及典型的几种均衡算法。分别采用稀疏多径信道和混合相位信道对几种典型的自适应算法和盲均衡算法的均方误差(MSE)性能进行了仿真比较,结果显示,判决反馈均衡器(DFE)结构的算法在以上复杂水声环境中均衡效果良好;采用稀疏多径相位旋转复信道对典型的自适应、盲均衡算法进行了仿真比较,结果表明,在相同的条件下,自适应算法受相位的影响较小,收敛速度快于盲均衡算法。消声水池实验表明了带二阶数字锁相环(DPLL)和DFE结构的均衡算法均具有较好的载波恢复性能,实现了对相位偏差的跟踪,提高了克服多径效应和多普勒频移补偿的能力。

A Fractional-N CMOS DPLL with Self-Calibration

A digital phase-locked loop （DPLL） based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works from 60 to 600MHz at a supply voltage of 1.8V. It also features a fraetional-N synthesizer with digital 2nd-order sigma-delta noise shaping, which can achieve a short lock time,a high frequency resolution,and an improved phase-noise spectrum. The DPLL has been implemented in SMIC 0. 18μm 1.8V 1P6M CMOS technology. The peak-to-peak jitter is less than 0. 8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider.

微弱信号检测与锁定放大电路

介绍了一种微弱信号的检测与锁定放大方法。通过模拟锁相环工作锁定待检微弱信号的频率,利用控制器测量该锁相环的输出频率,并根据该频率值控制直接数字合成电路产生同频信号,该信号作为相关检测所需的参考信号。系统采用乘法器和积分电路实现相关检测,通过步进调整参考信号的相位,使互相关值最大,获得与被测信号同频同相的再生信号,从而实现微弱信号的检测与放大。该方法能够实现频率检测及幅度检测等功能。经实验测试表明:在低信噪比条件下,该方法仍具有较好的线性测量特性和较高的准确度,可实现任意波形的微弱信号自动检测和再生放大。

Low spurious noise frequency synthesis based on a DDS-driven wideband PLL architecture

An S-band frequency synthesizer for a stepped-frequency radar is presented. This frequen- cy synthesizer is based on a direct digital synthesizer （ DDS ） -driven wideband phase-locked loop （PLL） architecture which can achieve low spurious noise and rapid frequency hopping simultaneous- ly. The mechanism of introducing high level spurs by the images of DDS digital to analog convertor （DAC） output is analyzed. A novel DDS frequency planning method is proposed to ensure low col- ored noise within the entire bandwidth. The designed output frequency range is 3. 765 -4. 085 GHz, and the step size is 5 MHz with frequency agility of less than 1 μs. Measured results demonstrate that the average spurious free dynamic range （SFDR） is about 64 dBc in a 320 MHz bandwidth.

A time-domain digitally controlled oscillator composed of a free running ring oscillator and flying-adder

A time-domain digitally controlled oscillator （DCO） is proposed. The DCO is composed of a free-running ring oscillator （FRO） and a two lap-selectors integrated flying-adder （FA）. With a coiled cell array which allows uniform loading capacitances of the delay cells, the FRO produces 32 outputs with consistent tap spacing for the FA as reference clocks. The FA uses the outputs from the FRO to generate the output of the DCO according to the control number, resulting in a linear dependence of the output period, instead of the frequency on the digital controlling word input. Thus the proposed DCO ensures a good conversion linearity in a time-domain, and is suitable for time-domain all-digital phase locked loop applications. The DCO was implemented in a standard 0.13μm digital logic CMOS process. The measurement results show that the DCO has a linear and monotonic tuning curve with gain variation of less than 10%, and a very low root mean square period jitter of 9.3 ps in the output clocks. The DCO works well at supply voltages ranging from 0.6 to 1.2 V, and consumes 4 mW of power with 500 MHz frequency output at 1.2 V supply voltage.

Steady-State Performance of Kalman Filter for DPLL

For certain system models, the structure of the Kalman filter is equivalent to a second-order vari- able gain digital phase-locked loop （DPLL）. To apply the knowledge of DPLLs to the design of Kalman filters this paper studies the steady-state performance of Kalman filters for these system models. The results show that the steady-state Kalman gain has the same form as the DPLL gain. An approximate simple form for the steady-state Kalman gain is used to derive an expression for the equivalent loop bandwidth of the Kalman filter as a function of the process and observation noise variances. These results can be used to analyze the steady-state performance of a Kalman filter with DPLL theory or to design a Kalman filter model with the same steady-state performance as a given DPLL.