The closed-loop stability issue of finite-precision realizations was investigated for digital control-lers implemented in block-floating-point format. The controller coefficient perturbation was analyzed resultingfrom...The closed-loop stability issue of finite-precision realizations was investigated for digital control-lers implemented in block-floating-point format. The controller coefficient perturbation was analyzed resultingfrom using finite word length (FWL) block-floating-point representation scheme. A block-floating-point FWL closed-loop stability measure was derived which considers both the dynamic range and precision. To facilitate the design of optimal finite-precision controller realizations, a computationally tractable block-floating-point FWL closed-loop stability measure was then introduced and the method of computing the value of this measure for a given controller realization was developed. The optimal controller realization is defined as the solution that maximizes the corresponding measure, and a numerical optimization approach was adopted to solve the resulting optimal realization problem. A numerical example was used to illustrate the design procedure and to compare the optimal controller realization with the initial realization.展开更多
A small-signal model of current programmed mode pulse width modulation converter including the equivalent sampling effect is introduced and analyzed. In this model, an addition pole is brought out by the sampling effe...A small-signal model of current programmed mode pulse width modulation converter including the equivalent sampling effect is introduced and analyzed. In this model, an addition pole is brought out by the sampling effect in the current loop gain, and it affects dynamic bandwidth and stability of the inner current loop. By selecting the appropriate stability parameter which determines the additional pole and describes the degree of peaking in closed loop transfer function, a control model of current programmed full bridge arc welding inverter with maximum frequency bandwidth and stability can be obtained. Small and large amplitude pulse current outputs are employed in simulations and experiments and results validate the design method.展开更多
A digital controller IC for the flyback converter with primary-side feedback is proposed. The controller is used for adapter charger or LED driver applications. To obtain high accuracy for the primary-side feedback, a...A digital controller IC for the flyback converter with primary-side feedback is proposed. The controller is used for adapter charger or LED driver applications. To obtain high accuracy for the primary-side feedback, a digital primary-side sensing technology is adopted, which can auto-track the knee point of the primary auxiliary winding voltage. Furthermore, an internal digital compensator eliminates the need for external loop compensation components while achieving excellent line and load regulation. The controller could output both constant voltage and constant current depending on the load current. Pulse width modulation and pulse frequency modulation are used in constant voltage mode while quasi-resonant control is used in constant current mode. The digital controller is validated by using FPGA.展开更多
A modified four-dimensional linear active disturbance rejection control(LADRC)strategy is proposed for a dual three-phase permanent magnet synchronous generator(DTP-PMSG)system to reduce cross-coupling between the d a...A modified four-dimensional linear active disturbance rejection control(LADRC)strategy is proposed for a dual three-phase permanent magnet synchronous generator(DTP-PMSG)system to reduce cross-coupling between the d and q axis currents in the d-q subspace and harmonic currents in the x-y subspace.In the d-q subspace,the proposed strategy uses a model-based LADRC to enhance the decoupling effect between the d and q axes and the disturbance rejection ability against parameter variation.In the x-y subspace,the 5th and 7th harmonic current suppression abilities are improved by using quasi-resonant units parallel to the extended state observer of the traditional LADRC.The proposed modified LADRC strategy improved both the steady-state performance and dynamic response of the DTP-PMSG system.The experimental results demonstrate that the proposed strategy is both feasible and effective.展开更多
This paper presents a novel digital dual-loop control scheme of the PWM(PUlse width modulate)inverter. Deadbeat control technique are employed to enhance the performance. Half switching period delayed sampling and con...This paper presents a novel digital dual-loop control scheme of the PWM(PUlse width modulate)inverter. Deadbeat control technique are employed to enhance the performance. Half switching period delayed sampling and control timing strategy is used to improve the system dynamic response. Simulation and experimental results presented in the paper verified the validity of the proposed control scheme.展开更多
In order to control the lateral motion of a jet trencher which is important for stable trenching operation,the oscillation characteristics of the jet trencher are researched. The jet trencher is simplified into a sing...In order to control the lateral motion of a jet trencher which is important for stable trenching operation,the oscillation characteristics of the jet trencher are researched. The jet trencher is simplified into a single degree of freedom model with restoring and damping force. The nonlinear mathematical model of the trencher laterally oscillating in ocean currents is established,and its approximate analytical solution is obtained.Results show that the analytical solution has small differences with numerical solution based on the fourth-order Runge-Kutta method and can effectively describe the underwater oscillation. A double-loop PID controller is designed to control the lateral motion displacement of the trencher to return to the center of the pipeline route which is effective and robust for the propulsion system.展开更多
A low jitter All-Digital Phase-Locked Loop(ADPLL) used as a clock generator is designed.The Digital-Controlled Oscillator(DCO) for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable.Ba...A low jitter All-Digital Phase-Locked Loop(ADPLL) used as a clock generator is designed.The Digital-Controlled Oscillator(DCO) for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable.Based on the Impulse Sensitivity Function(ISF) analysis,an effective way is proposed to reduce the ADPLL's jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one.The ADPLL is implemented in a 0.18μm CMOS process with 1.8V supply voltage,occupies 0.046mm2 of on-chip area.According to the measured results,the ADPLL can operate from 108MHz to 304MHz,and the peak-to-peak jitter is 139ps when the DCO's output frequency is 188MHz.展开更多
Renewable energy sources require switching regulators as an interface to a load with high efficiency, small size, proper output regulation, and fast transient response. Moreover, due to the nonlinear behavior and swit...Renewable energy sources require switching regulators as an interface to a load with high efficiency, small size, proper output regulation, and fast transient response. Moreover, due to the nonlinear behavior and switching nature of DC-DC power electronic converters, there is a need for high-performance control strategies. This work summarized the dynamic behavior for the three basic switch-mode DC-DC power converters operating in continuous conduction mode, </span><i><span style="font-family:Verdana;">i.e.</span></i><span style="font-family:Verdana;"> buck, boost, and buck-boost. A controller was designed using loop-shaping based on current-mode control that consists of two feedback loops. A high-gain compensator with wide bandwidth was used in the inner current loop for fast transient response. A proportional-integral controller was used in the outer voltage loop for regulation purposes. A proce</span><span style="font-family:Verdana;">dure was proposed for the parameters of the controller that ensures closed-loop</span><span style="font-family:Verdana;"> stability and output voltage regulation. The design-oriented analysis was applied to the three basic switch-mode DC-DC power converters. Experimental results were obtained for a switching regulator with a boost converter of 150 W, which exhibits non-minimum phase behavior. The performance of the controller was tested for voltage regulation by applying large load changes.展开更多
文摘The closed-loop stability issue of finite-precision realizations was investigated for digital control-lers implemented in block-floating-point format. The controller coefficient perturbation was analyzed resultingfrom using finite word length (FWL) block-floating-point representation scheme. A block-floating-point FWL closed-loop stability measure was derived which considers both the dynamic range and precision. To facilitate the design of optimal finite-precision controller realizations, a computationally tractable block-floating-point FWL closed-loop stability measure was then introduced and the method of computing the value of this measure for a given controller realization was developed. The optimal controller realization is defined as the solution that maximizes the corresponding measure, and a numerical optimization approach was adopted to solve the resulting optimal realization problem. A numerical example was used to illustrate the design procedure and to compare the optimal controller realization with the initial realization.
文摘A small-signal model of current programmed mode pulse width modulation converter including the equivalent sampling effect is introduced and analyzed. In this model, an addition pole is brought out by the sampling effect in the current loop gain, and it affects dynamic bandwidth and stability of the inner current loop. By selecting the appropriate stability parameter which determines the additional pole and describes the degree of peaking in closed loop transfer function, a control model of current programmed full bridge arc welding inverter with maximum frequency bandwidth and stability can be obtained. Small and large amplitude pulse current outputs are employed in simulations and experiments and results validate the design method.
文摘A digital controller IC for the flyback converter with primary-side feedback is proposed. The controller is used for adapter charger or LED driver applications. To obtain high accuracy for the primary-side feedback, a digital primary-side sensing technology is adopted, which can auto-track the knee point of the primary auxiliary winding voltage. Furthermore, an internal digital compensator eliminates the need for external loop compensation components while achieving excellent line and load regulation. The controller could output both constant voltage and constant current depending on the load current. Pulse width modulation and pulse frequency modulation are used in constant voltage mode while quasi-resonant control is used in constant current mode. The digital controller is validated by using FPGA.
基金Supported by the National Science Fund for Distinguished Young Scholars under Grant 52025073 and the Zhenjiang Key Research Program under Grant GY2020011.
文摘A modified four-dimensional linear active disturbance rejection control(LADRC)strategy is proposed for a dual three-phase permanent magnet synchronous generator(DTP-PMSG)system to reduce cross-coupling between the d and q axis currents in the d-q subspace and harmonic currents in the x-y subspace.In the d-q subspace,the proposed strategy uses a model-based LADRC to enhance the decoupling effect between the d and q axes and the disturbance rejection ability against parameter variation.In the x-y subspace,the 5th and 7th harmonic current suppression abilities are improved by using quasi-resonant units parallel to the extended state observer of the traditional LADRC.The proposed modified LADRC strategy improved both the steady-state performance and dynamic response of the DTP-PMSG system.The experimental results demonstrate that the proposed strategy is both feasible and effective.
文摘This paper presents a novel digital dual-loop control scheme of the PWM(PUlse width modulate)inverter. Deadbeat control technique are employed to enhance the performance. Half switching period delayed sampling and control timing strategy is used to improve the system dynamic response. Simulation and experimental results presented in the paper verified the validity of the proposed control scheme.
基金Sponsored by the High Technology Ship Research and Program of Ministry of Industry and Information Technology of the People's Republic of China(Grant No.539[2012])the Specialized Research Fund for the Doctoral Program of Higher Education of China(Grant No.20120073120014)
文摘In order to control the lateral motion of a jet trencher which is important for stable trenching operation,the oscillation characteristics of the jet trencher are researched. The jet trencher is simplified into a single degree of freedom model with restoring and damping force. The nonlinear mathematical model of the trencher laterally oscillating in ocean currents is established,and its approximate analytical solution is obtained.Results show that the analytical solution has small differences with numerical solution based on the fourth-order Runge-Kutta method and can effectively describe the underwater oscillation. A double-loop PID controller is designed to control the lateral motion displacement of the trencher to return to the center of the pipeline route which is effective and robust for the propulsion system.
文摘A low jitter All-Digital Phase-Locked Loop(ADPLL) used as a clock generator is designed.The Digital-Controlled Oscillator(DCO) for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable.Based on the Impulse Sensitivity Function(ISF) analysis,an effective way is proposed to reduce the ADPLL's jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one.The ADPLL is implemented in a 0.18μm CMOS process with 1.8V supply voltage,occupies 0.046mm2 of on-chip area.According to the measured results,the ADPLL can operate from 108MHz to 304MHz,and the peak-to-peak jitter is 139ps when the DCO's output frequency is 188MHz.
文摘Renewable energy sources require switching regulators as an interface to a load with high efficiency, small size, proper output regulation, and fast transient response. Moreover, due to the nonlinear behavior and switching nature of DC-DC power electronic converters, there is a need for high-performance control strategies. This work summarized the dynamic behavior for the three basic switch-mode DC-DC power converters operating in continuous conduction mode, </span><i><span style="font-family:Verdana;">i.e.</span></i><span style="font-family:Verdana;"> buck, boost, and buck-boost. A controller was designed using loop-shaping based on current-mode control that consists of two feedback loops. A high-gain compensator with wide bandwidth was used in the inner current loop for fast transient response. A proportional-integral controller was used in the outer voltage loop for regulation purposes. A proce</span><span style="font-family:Verdana;">dure was proposed for the parameters of the controller that ensures closed-loop</span><span style="font-family:Verdana;"> stability and output voltage regulation. The design-oriented analysis was applied to the three basic switch-mode DC-DC power converters. Experimental results were obtained for a switching regulator with a boost converter of 150 W, which exhibits non-minimum phase behavior. The performance of the controller was tested for voltage regulation by applying large load changes.