THE DESIGN OF AN ALL-DIGITAL PHASE-LOCKED LOOP WITH LOW JITTER BASED ON ISF ANALYSIS

A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.

A LOW POWER TIME-TO-DIGITAL CONVERTER FOR ALL-DIGITAL PHASE-LOCKED LOOP

Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.

A novel high precision Doppler frequency estimation method based on the third-order phase-locked loop

In deep space exploration,many engineering and scientific requirements require the accuracy of the measured Doppler frequency to be as high as possible.In our paper,we analyze the possible frequency measurement points of the third-order phase-locked loop(PLL)and find a new Doppler measurement strategy.Based on this finding,a Doppler frequency measurement algorithm with significantly higher measurement accuracy is obtained.In the actual data processing,compared with the existing engineering software,the accuracy of frequency of 1 second integration is about 5.5 times higher when using the new algorithm.The improved algorithm is simple and easy to implement.This improvement can be easily combined with other improvement methods of PLL,so that the performance of PLL can be further improved.

A Digital Phase Locked Loop Speed Control of Three Phase Induction Motor Drive: Performances Analysis

This paper deals with performance analysis and implementation of a three phase inverter fed induction motor (IM) drive system. The closed loop control scheme of the drive utilizes the Digital Phase Locked Loop (DPLL). The DPLL is safely implemented all around the well known integrated circuit DPLL 4046. An ex-perimental verification is carried out on one kw scalar controlled IM system drives for a wide range of speeds and loads appliance. This presents a simple and high performance solution for industrial applications.

Dynamic Free-Spectral-Range Measurement for Fiber Resonator Based on Digital-Heterodyne Optical Phase-Locked Loop

We propose a novel scheme, based on digital-heterodyne optical phase-locked loop with whole-fiber circuit, to dynamically measure the free-spectral-range of a fiber resonator. The optical phase-locked loop is established with a differential frequency-modulation module consists of a pair of acousto-optic modulators. The resonance-tracking loop is derived with the Pound-Drever-Hall technique for locking the heterodyne frequency of the OPLL on the frequency difference between adjacent resonance modes. A stable locking accuracy of about 7 × 10?9 and a dynamic locking accuracy of about 5 × 10?8 are achieved with the FSR of 8.155 MHz, indicating a bias stability of the resonator fiber optic gyro of about 0.1?/h with 10 Hz bandwidth. In addition, the thermal drift coefficient of the FSR is measured as 0.1 Hz/?C. This shows remarkable potential for realizing advanced optical measurement systems, such as the resonant fiber optic gyro, and so on.

Self-Balanced Charge Pump with Fast Lock Circuit

A self-balanced charge pump （CP） with fast lock circuit to achieve nearly zero phase error is proposed and analyzed. The proposed CP is designed based on the SMIC 0.25μm 1P5M complementary metal oxide semiconductor （CMOS） process with a 2.5 V supply voltage, HSPICE simulation shows that even if the mismatch of phase/frequency detector （PFD） was beyond 10%, the charge pump could still keep nearly zero phase error, Incorporated fast lock circuit can shorten start-up time to below 300 ns.

A Low Phase Noise Ring-VCO Based PLL Using Injection Locking for ZigBee Applications

A low power low phase noise frequency synthesizer with subharmonic injection locking is proposed for ZigBee applications. The PLL is based on a ring VCO to decrease area and production cost. In order to improve phase noise performance, a high frequency injection signal of which frequency varies with channel number is used. The circuit is designed in TSMC 0.18 μm CMOS technology and simulated in ADS (Advanced Design System). The phase noise at 3.5 and 10 MHz offsets is -116 and -118 dBc/Hz, respectively, and total circuit consumes 2.2 mA current.

2.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit

A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency detector （PFD） is used in the PLL. The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW.

A Σ-Δ Fractional-N PLL Frequency Synthesizer with AFC for SRD Applications

A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise. The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly,an out-band phase noise of -139dBc/Hz at 3MHz offset frequency, and a fractional spur of less than - 60dBc. The chip area is 1.5mm × 1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage.

2.7-4.0 GHz PLL with dual-mode auto frequency calibration for navigation system on chip

A 2.7-4.0 GHz dual-mode auto frequency calibration(AFC) fast locking PLL was designed for navigation system on chip(SoC). The SoC was composed of one radio frequency(RF) receiver, one baseband and several system control parts. In the proposed AFC block, both analog and digital modes were designed to complete the AFC process. In analog mode, the analog part sampled and detected the charge pump output tuning voltage, which would give the indicator to digital part to adjust the voltage control oscillator(VCO) capacitor bank. In digital mode, the digital part counted the phase lock loop(PLL) divided clock to judge whether VCO frequency was fast or slow. The analog and digital modes completed the auto frequency calibration function independently by internal switch. By designing a special switching algorithm, the switch of the digital and analog mode could be realized anytime during the lock and unlock detecting process for faster and more stable locking. This chip is fabricated in 0.13 μm RF complementary metal oxide semiconductor(CMOS) process, and the VCO supports the frequency range from 2.7 to 4.0 GHz. Tested 3.96 GHz frequency phase noise is -90 d Bc/Hz@100 k Hz frequency offset and -120 d Bc/Hz@1 MHz frequency offset. By using the analog mode in lock detection and digital mode in unlock detection, tested AFC time is less than 9 μs and the total PLL lock time is less than 19 μs. The SoC acquisition and tracking sensitivity are about-142 d Bm and-155 d Bm, respectively. The area of the proposed PLL is 0.35 mm^2 and the total SoC area is about 9.6 mm^2.

TDTL Based Frequency Synthesizers with Auto Sensing Technique

This paper presents a frequency synthesizer architecture based on the time delay digital tanlock loop (TDTL). The loop is of the first order type. The synthesizer architecture includes an adaptation mechanism to keep the complete system in lock. The mechanism uses a frequency sensing structure to control critical TDTL parameters responsible for locking. Both integer and fractional multiples of the loop reference frequency are synthesized by the new architecture. The ability of the TDTL based frequency synthesizer to respond to sudden variations in the system input frequency is studied. The results obtained indicate the proposed synthesizer has a robust performance and is capable of responding to those changes provided that they are within the bounds of its locking region.

电网故障下含直驱风电机组的电力系统频率动态响应分析

电网受扰后基于模型解析的频率响应分析对电力系统安全评估与紧急控制具有重要意义。电网发生故障时,直驱风电机组(DDWT)并网点电压幅值跌落引发控制器暂态响应,同时电压相位突变引发锁相暂态响应,锁相暂态响应又通过变流器控制传导产生功率控制误差,可能导致现有以负荷突变场景为对象的频率特性分析产生较大偏差。为此,提出了电网故障下DDWT锁相偏差的量化方法;解析了锁相偏差经DDWT变流器控制的传导路径,提出了锁相暂态响应导致DDWT功率控制误差的机理及其计算方法;建立了电网故障下含DDWT的电力系统频率响应模型,提出了锁相暂态响应影响下系统频率变化率和最大频率偏差的计算方法,解析了电网故障下考虑DDWT功率控制误差的电力系统频率动态响应特性,并通过算例分析验证了所提方法的有效性。

基于SSO多扰动输入机理分析的DFIG-GSC功率振荡抑制策略研究

电网次同步振荡(SSO)已成为桎梏新能源发展的主要问题之一,针对SSO下双馈感应发电机(DFIG)中网侧变流器(GSC)的功率振荡问题展开研究。首先,建立SSO对GSC的多扰动输入数学模型,探究不同扰动输入的性质以及其对GSC系统的影响,明确了针对物理量扰动以及信号扰动分别采用补偿与滤除两种不同的抑制方法。其次,针对锁相环(PLL)输出误差经过坐标变换产生耦合振荡的问题,建立PLL输出误差角度的频域数学模型,并通过设计一种改进PLL消除其输出误差对GSC的信号扰动影响。同时,设计一种准谐振控制器的自适应算法,并提出基于自适应准谐振控制器的DFIG-GSC功率振荡抑制策略,消除SSO对GSC的物理扰动影响;最后,通过搭建具有SSO模拟环境的DFIG实验平台,验证本文所提控制策略的有效性。

带残余频偏的软扩频信号伪码序列盲估计

针对带残余频偏的软扩频信号伪码序列盲估计难的问题,提出一种奇异值分解(singular value decomposition,SVD)结合全数字锁相环(digital phase locked loop,DPLL)的方法。所提方法首先对待处理信号通过不重叠分段生成数据矩阵,每段信号长度为一倍伪码周期;然后利用其自相关矩阵的右上角元素估计失步点进行同步,并且在重新计算自相关矩阵后根据较大特征值个数估计进制数;最后通过多次快速SVD算法结合DPLL最终实现伪码序列的盲估计。仿真结果显示,所提方法在低信噪比条件下可以有效估计出带残余频偏的软扩频信号的伪码序列,并且性能优于其他对比方法。

用于新型符号的频偏补偿和解调的算法与电路

为提高传统脉冲位置调制(pulse position modulation,PPM)符号的频谱效率,提出了一种新型码片内4-PPM符号调制方法,在实现1 Gbit/s通信速率的同时,又大大减少所需频谱资源。可在解调时,该符号调制的误码率性能受到发射端时钟和接收端本地时钟之间的频率偏移的极大影响。针对此问题,又提出了一种在模拟域对该符号进行频偏补偿,并实现符号同步和高速数据解调的算法与电路。该电路系统通过消除接收数据和本地时钟的初始相差、提取两者的频偏信息、周期性改变本地时钟的瞬时相位3步实现频偏补偿,并同时在第3步利用本地时钟对接收数据进行解调。为提高相位插值器(phase interpolator,PI)的线性度,本文将延迟锁定环与PI相结合。在2π的插值范围内,实现插值区间32个,插值步长992个,分辨率2.016 ps,最大差分非线性(differential nonlinearity,DNL)0.183°,最大积分非线性(integral nonlinearity,INL)0.325°。此外,本文提出的相位控制算法有效避免了由电流毛刺所引起的输出相位突变。电路基于UMC 40 nm CMOS RF LP工艺进行设计与仿真。仿真结果表明:本文所提出的算法与电路,在典型工艺角下,将接收数据和本地时钟间的50×10^(-6)频率偏差度降至1.03×10^(-6),频偏补偿准确度达到97.94%,并实现1 Gbit/s的解调速率。该方法对高速PPM数据同步与解调具有良好的工程应用价值。

低抖动电荷泵锁相环设计及其Simulink建模仿真

随着集成电路工艺技术的进步,电路工作频率越来越高,对时钟信号的抖动和相噪也提出了更高的要求。针对锁相环电路参数多、结构复杂、瞬态仿真耗时长等问题,通过建立电荷泵锁相环系统环路数学模型,并运用MATLAB/Simulink对其进行负反馈系统建模,实现对电荷泵锁相环的快速动态仿真。在TSMC 65 nm CMOS工艺节点下,完成了锁相环的电路设计、版图绘制、物理验证并提取寄生参数及后仿真,得到一款典型值:输入频率为30 MHz,锁定频率1.5 GHz的低抖动电荷泵锁相环。后仿真结果表明该PLL电路性能指标良好,在典型值条件下,PLL的锁定时间为10μs,锁定时峰峰值抖动为2.68 ps,时钟信号占空比为45%。

基于主动式阻尼的混合式步进电机转速振荡抑制控制

混合式步进电机因其特殊的机械结构导致自身阻尼极小,在实际运行过程中会发生振荡过大,甚至失步的问题。为提高混合式步进电机的控制品质,提出一种基于主动式阻尼的步进电机转速振荡抑制方法。首先,将电机模型转化至同步旋转dq坐标系,将电流i_d控制恒为额定电流,利用位置误差和速度误差调节电流i_q生成瞬时转矩,抑制电机运行时存在的振荡现象。其次,为实现电机闭环反馈控制,提出一种将同步频率提取滤波器(SFF)与三阶锁相环(PLL~3rd)相结合的无传感器控制方法。SFF可以滤除反电动势信号中的高次谐波,PLL~3rd能消除转速变化过程中的稳态误差。实验证明,该方法有效抑制了步进电机运行过程中的振荡现象,提升了电机的运行品质。

计及锁相环动态的单相并网逆变器建模及稳定性研究综述

随着可再生能源渗透率的提高,电网呈现出高电网阻抗的弱电网甚至极弱电网特征,锁相环与电网阻抗交互作用将恶化跟网型逆变器低频稳定性。近年来,诸多文献针对单相跟网型逆变器中的低频振荡问题进行了研究,但缺乏对现有成果系统性地梳理和总结,难以明确进一步的研究重点。为此,该文首先梳理和评述现有计及锁相环影响的逆变器建模及稳定性分析方法,直观地阐述锁相环引起的负阻效应对系统低频稳定性的影响机制,并在此基础上,从改进电流控制环和锁相环角度,系统性地归纳和分析现有各种低频鲁棒性提高方法。最后,总结现有研究在稳定性分析及鲁棒性改进上的不足及研究关键点和难点,指出进一步的研究方向。

基于自适应增强型复系数滤波器的多电飞机变频电网状态估计

多电飞机的电网是一种典型的孤岛微网,具有360~800 Hz的宽频率工作范围,传统恒定频率电网同步方法的动态性能在飞机变频电网中有所不足。为了准确估计飞机变频电网的电网状态,结合自适应模块,对增强型复系数滤波器锁相环进行改进,设计了一种适应于MEA变频电网的自适应增强型复系数滤波器锁相环结构(AECCF-PLL)。分析了其传递函数与阶跃响应之间的关系,推导了模型参数与频率的关系,建立了频率自适应模块,满足飞机变频交流电网状态估计对稳定性和快速性的要求。实验结果表明,在飞机变频电网含有大小频率跳变、谐波、斜坡等扰动情况时,提出的AECCF-PLL可以实现对电网状态的快速稳定估计。

基于声光调制器的光学锁相环He-Ne激光稳频方法研究

报道了一种基于声光调制器与光学锁相环相结合的高稳定度激光稳频方法,用于提高热稳频He-Ne激光器的频率稳定度和准确度。为了克服全内腔热稳频He-Ne激光精密调谐困难的缺点,发展了基于声光调制器两次移频的频率调谐光路,有效地消除声光调制器移频光束路径对衍射角θ的依赖。自行研制了具有高灵敏度与捕获带宽的光学锁相环系统,利用声光调制器的高频率响应特性实现热稳频He-Ne激光高速、准确的锁定。成功实现了热稳频He-Ne激光器偏频锁定至碘稳频HeNe激光器。实验结果表明,环路锁定后拍频频率波动在±0.2 Hz范围内,频率抖动的标准差为0.04。偏置频率为30 MHz时,系统在1 s和1000 s积分时间的相对阿伦方差分别为3.3×10^(-9)和1.4×10^(-12)。系统锁定后,压缩后的拍频线宽小于2 kHz。该研究表明,采用基于声光调制器与光学锁相环相结合的激光稳频方法可以实现亚赫兹级的激光频差控制,通过将热稳频He-Ne激光器偏频锁定至高稳定度的参考激光源可以显著提升其频率稳定度和准确度。