A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC

This paper presents a high speed ROM-less direct digital frequency synthesizer （DDFS） which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic （CML） is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm^2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0℃.

A high speed direct digital frequency synthesizer based on multi-channel structure

This paper presents a direct digital frequency synthesizer （DDFS） for high speed application based on multi-channel structure. This DDFS has phase resolution of 32 bits and magnitude resolution of 12 bits. In order to ensure the high speed and high resolution at the same time, the multi-channel sampling technique is used and a 12 bits linear digital-to-analog converter is implemented. The chip is fabricated in TSMC 130 nm CMOS technology with active area of 0.89 x 0.98 mm2 and total power consumption of 300 mW at a single 1.2 V supply voltage. The maximum operating speed is up to 2.0 GHz at room temperature.

A high-performance MUX-direct digital frequency synthesizer with quarter ROMs

This paper presents a detailed description of a high-performance direct digital frequency synthesizer （DDFS） using optimized quarter ROMs. To improve the working frequency and spectral purity, an original quarter ROMs structure in 0.13 μm CMOS is brought forward and implemented. The working frequency is increased by 40% compared with Yuan Ling＇s methodIll of implementing a segmented DAC based DDFS. It has been implemented in 0.13 μm CMOS technology. The DDFS has a resolution of 10 bits with a measured SFDR 54 dBc. Its maximum operating frequency is 1.2 GHz by using six pipelining stages. Analytical investigation of improving spectral performances by using dual-slope approximation and pipeline is also presented.

DDFS spurious signals due to amplitude quantization in absence of phase-accumulator truncation

Spurious signals in direct digital frequency synthesizers （DDFSs） are partly caused by amplitude quantization and phase truncation, which affect their application to many wireless telecommunication systems. These signals are deterministic and periodic in the time domain, so they appear as line spectra in the frequency domain. Two types of spurious signals due to amplitude quantization are exactly formulated and compared in the time and frequency domains respectively. Then the frequency spectra and power levels of the spurious signals due to amplitude quantization in the absence of phase-accumulator truncation are emphatically analyzed, and the effects of the DDFS parameter variations on the spurious signals are thoroughly studied by computer simulation. And several important conclusions are derived which can provide theoretical support for parameter choice and spurious performance evaluation in the application of DDFSs.