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A Strong Anti-Jamming Algorithm Based on FPGA for Estimating Loop Delay in Digital Predistortion System
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作者 Feng-Jun Li Jing-Fu Bao +1 位作者 Hong-Yun Huang Shao-Chun Jin 《Journal of Electronic Science and Technology》 CAS 2012年第4期358-362,共5页
At present what are the key points focused in the research of loop-delay estimation for the digital predistorter in the radio frequency (RF) power amplifier system is reducing its complexity of engineering realizati... At present what are the key points focused in the research of loop-delay estimation for the digital predistorter in the radio frequency (RF) power amplifier system is reducing its complexity of engineering realization and improving anti-jamming ability and computational speed. Besides, opening up its application scope should be contained. For these targets, a novel method including integer loop delay estimation and fractional part is proposed. The integer part applies amplitude-difference summation function and the fractional one adopts the method of finite impulse response (FIR) linear interpolation. The algorithm finds wide applications. What is more, strong anti-jamming ability and low complexity are also its merits. Simulation results support the above opinion. Digital predistortion (DPD) system based on this algorithm achieves good performance. 展开更多
关键词 BASEBAND digital predistortion linearinterpolation loop delay estimation power amplifier.
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A LOW POWER TIME-TO-DIGITAL CONVERTER FOR ALL-DIGITAL PHASE-LOCKED LOOP 被引量:1
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作者 Yu Guangming Wang Yu Yang Huazhong 《Journal of Electronics(China)》 2011年第3期402-408,共7页
Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to abo... Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique. 展开更多
关键词 Low power Power management All-digital Phase-Locked loop (ADPLL) Time-to-digital Converter (TDC)
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A Digital Phase Locked Loop Speed Control of Three Phase Induction Motor Drive: Performances Analysis
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作者 Ben Hamed Mouna Sbita Lassaad 《Energy and Power Engineering》 2011年第1期61-68,共8页
This paper deals with performance analysis and implementation of a three phase inverter fed induction motor (IM) drive system. The closed loop control scheme of the drive utilizes the Digital Phase Locked Loop (DPLL).... This paper deals with performance analysis and implementation of a three phase inverter fed induction motor (IM) drive system. The closed loop control scheme of the drive utilizes the Digital Phase Locked Loop (DPLL). The DPLL is safely implemented all around the well known integrated circuit DPLL 4046. An ex-perimental verification is carried out on one kw scalar controlled IM system drives for a wide range of speeds and loads appliance. This presents a simple and high performance solution for industrial applications. 展开更多
关键词 digital Phase Locked loop (DPLL) INDUCTION Motor SCALAR Strategy Speed DRIVES and Load APPLIANCE
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THE DESIGN OF AN ALL-DIGITAL PHASE-LOCKED LOOP WITH LOW JITTER BASED ON ISF ANALYSIS
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作者 Deng Xiaoying Yang Jun Shi Longxing Chen Xin 《Journal of Electronics(China)》 2008年第5期673-678,共6页
A low jitter All-Digital Phase-Locked Loop (ADPLL) used as a clock generator is designed. The Digital-Controlled Oscillator (DCO) for this ADPLL is a seven-stage ring oscillator with the delay of each stage change... A low jitter All-Digital Phase-Locked Loop (ADPLL) used as a clock generator is designed. The Digital-Controlled Oscillator (DCO) for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function (ISF) analysis, an effective way is proposed to reduce the ADPLL's jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO's output frequency is 188MHz. 展开更多
关键词 All-digital Phase Locked loop (ADPLL) digital Controlled Oscillator (DCO) Impulse Sensitivity Function (ISF) Thermal noise JITTER
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Fault Waveform Regenerator and Its Digital Closed-Loop Modification Technique
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作者 Xiaoming Sun 《Journal of Power and Energy Engineering》 2019年第2期14-26,共13页
In order to provide a novel and more effective alternative to the commonly used relay protection testing device that outputs only the sinusoidal testing signals, the concept of fault waveform regenerator is proposed i... In order to provide a novel and more effective alternative to the commonly used relay protection testing device that outputs only the sinusoidal testing signals, the concept of fault waveform regenerator is proposed in this paper, together with its hardware structure and software flow chart. Fault waveform regenerator mainly depends on its power amplifiers (PAs) to regenerate the fault waveforms recorded by digital fault recorder (DFR). To counteract the PA’s inherent nonlinear distortions, a digital closed-loop modification technique that is different from the predistortion technique is conceived. And the experimental results verify the effectiveness of the fault waveform regenerator based on the digital closed-loop modification technique. 展开更多
关键词 Fault WAVEFORM REGENERATOR digital CLOSED-loop MODIFICATION TECHNIQUE Power Amplifier Relay Protection Testing Device
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Dynamic Free-Spectral-Range Measurement for Fiber Resonator Based on Digital-Heterodyne Optical Phase-Locked Loop
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作者 Hongchen Jiao Tao Wang +2 位作者 Heli Gao Lishuang Feng Honghao Ma 《Optics and Photonics Journal》 2021年第8期332-340,共9页
<div style="text-align:justify;"> We propose a novel scheme, based on digital-heterodyne optical phase-locked loop with whole-fiber circuit, to dynamically measure the free-spectral-range of a fiber re... <div style="text-align:justify;"> We propose a novel scheme, based on digital-heterodyne optical phase-locked loop with whole-fiber circuit, to dynamically measure the free-spectral-range of a fiber resonator. The optical phase-locked loop is established with a differential frequency-modulation module consists of a pair of acousto-optic modulators. The resonance-tracking loop is derived with the Pound-Drever-Hall technique for locking the heterodyne frequency of the OPLL on the frequency difference between adjacent resonance modes. A stable locking accuracy of about 7 × 10<sup>?9</sup> and a dynamic locking accuracy of about 5 × 10<sup>?8</sup> are achieved with the FSR of 8.155 MHz, indicating a bias stability of the resonator fiber optic gyro of about 0.1?/h with 10 Hz bandwidth. In addition, the thermal drift coefficient of the FSR is measured as 0.1 Hz/?C. This shows remarkable potential for realizing advanced optical measurement systems, such as the resonant fiber optic gyro, and so on. </div> 展开更多
关键词 Free Spectral Range Fiber Resonator Dynamic Measurement digital-Heterodyne Optical Phase-Locked loop Resonant Fiber Optic Gyro
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Digital Signal Processing Based Real Time Vehicular Detection System 被引量:3
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作者 杨兆选 林涛 +2 位作者 李香萍 刘春义 高健 《Transactions of Tianjin University》 EI CAS 2005年第2期119-124,共6页
Traffic monitoring is of major importance for enforcing traffic management policies.To accomplish this task,the detection of vehicle can be achieved by exploiting image analysis techniques.In this paper,a solution is ... Traffic monitoring is of major importance for enforcing traffic management policies.To accomplish this task,the detection of vehicle can be achieved by exploiting image analysis techniques.In this paper,a solution is presented to obtain various traffic parameters through vehicular video detection system(VVDS).VVDS exploits the algorithm based on virtual loops to detect moving vehicle in real time.This algorithm uses the background differencing method,and vehicles can be detected through luminance difference of pixels between background image and current image.Furthermore a novel technology named as spatio-temporal image sequences analysis is applied to background differencing to improve detection accuracy.Then a hardware implementation of a digital signal processing (DSP) based board is described in detail and the board can simultaneously process four-channel video from different cameras. The benefit of usage of DSP is that images of a roadway can be processed at frame rate due to DSP′s high performance.In the end,VVDS is tested on real-world scenes and experiment results show that the system is both fast and robust to the surveillance of transportation. 展开更多
关键词 intelligent transportation system vehicular detection digital signal processing loop emulation background differencing
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A New Digital Image Encryption Algorithm Based on Improved Logistic Mapping and Josephus Circle
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作者 Zhiben Zhuang Jing Wang +2 位作者 Jingyi Liu Dingding Yang Shiqiang Chen 《Journal of Computer and Communications》 2018年第6期31-44,共14页
Digital image encryption based on Joseph circle and Chaotic system has become a hot spot in the research of image encryption. An encryption algorithm based on improved Josephus loop and logistic mapping is proposed to... Digital image encryption based on Joseph circle and Chaotic system has become a hot spot in the research of image encryption. An encryption algorithm based on improved Josephus loop and logistic mapping is proposed to scrambling blocks in this paper. At first, the original image is scrambled by using logistic mapping to obtain the encrypted image, and then the encrypted image is divided into many blocks. Finally, the position of the blocked image is scrambled by using the improved Josephus ring to get the encrypted image. According to the experiments, the information entropy of the encrypted image reaches 7.99 and the adjacent correlations in three directions are within ±0.1. The experimental results show that the proposed algorithm has advantages of large key space, high key sensitivity and can effectively resist the attacks of statistical analysis and gray value analysis. It has good encryption effect on digital image encryption. 展开更多
关键词 digital IMAGE ENCRYPTION IMAGE Block SCRAMBLING JOSEPHUS loop Logistic Mapping PIXEL SCRAMBLING
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Optimization of block-floating-point realizations for digital controllers with finite-word-length considerations
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作者 吴俊 胡协和 +1 位作者 陈生 褚健 《Journal of Zhejiang University Science》 EI CSCD 2003年第6期651-657,共7页
The closed-loop stability issue of finite-precision realizations was investigated for digital control-lers implemented in block-floating-point format. The controller coefficient perturbation was analyzed resultingfrom... The closed-loop stability issue of finite-precision realizations was investigated for digital control-lers implemented in block-floating-point format. The controller coefficient perturbation was analyzed resultingfrom using finite word length (FWL) block-floating-point representation scheme. A block-floating-point FWL closed-loop stability measure was derived which considers both the dynamic range and precision. To facilitate the design of optimal finite-precision controller realizations, a computationally tractable block-floating-point FWL closed-loop stability measure was then introduced and the method of computing the value of this measure for a given controller realization was developed. The optimal controller realization is defined as the solution that maximizes the corresponding measure, and a numerical optimization approach was adopted to solve the resulting optimal realization problem. A numerical example was used to illustrate the design procedure and to compare the optimal controller realization with the initial realization. 展开更多
关键词 digital controller Finite word length Block floating point Closed loop stability OPTIMIZATION
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Research into the sampling methods of digital beam position measurement
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作者 邬维浩 赵雷 +2 位作者 陈二雷 刘树彬 安琪 《Nuclear Science and Techniques》 SCIE CAS CSCD 2015年第3期71-76,共6页
A fully digital beam position monitoring system(DBPM) has been designed for SSRF(Shanghai Synchrotron Radiation Facility). As analog-to-digital converter(ADC) is a crucial part in the DBPM system, the sampling methods... A fully digital beam position monitoring system(DBPM) has been designed for SSRF(Shanghai Synchrotron Radiation Facility). As analog-to-digital converter(ADC) is a crucial part in the DBPM system, the sampling methods should be studied to achieve optimum performance. Different sampling modes were used and compared through tests. Long term variation among four sampling channels, which would introduce errors in beam position measurement, is investigated. An interleaved distribution scheme was designed to address this issue. To evaluate the sampling methods, in-beam tests were conducted in SSRF. Test results indicate that with proper sampling methods, a turn-by-turn(TBT) position resolution better than 1 μm is achieved, and the slow-acquisition(SA) position resolution is improved from 4.28 μm to 0.17 μm. 展开更多
关键词 采样方法 位置测量 数字波束 上海同步辐射装置 束流位置监测系统 位置分辨率 试验比较 抽样方法
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工科专业虚实结合实践教学方式应用研究 被引量:1
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作者 顾伟宏 张佳薇 +2 位作者 张妤 张澎涛 冷欣 《中国现代教育装备》 2024年第5期116-119,共4页
随着工科高等教育改革的推进和行业发展需求的变化,实践教学改革势在必行。针对工科专业实践教学现状,结合硬件在环和数字孪生两种实践教学手段,阐述虚实结合实践教学方式的优势。在此基础上对运动控制系统和可编程控制器两门课程的虚... 随着工科高等教育改革的推进和行业发展需求的变化,实践教学改革势在必行。针对工科专业实践教学现状,结合硬件在环和数字孪生两种实践教学手段,阐述虚实结合实践教学方式的优势。在此基础上对运动控制系统和可编程控制器两门课程的虚实结合实践教学应用进行分析讨论。实践表明,虚实结合实践教学方式对学生完成理论知识内化、提升实践能力和创新能力具有显著的促进作用。 展开更多
关键词 实践教学 虚实结合 数字孪生 硬件在环
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基于大创项目的应用技术开发实践——以数字电源教具设计为例
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作者 韩冬林 闫婧 梁坤仪 《天津中德应用技术大学学报》 2024年第2期70-75,共6页
针对教学环节中的难点和重点内容,基于dsPIC33CK256MP505数字信号控制器芯片,为开发新型的数字电源教具,在降压转换器的电路拓扑结构基础上,利用MplabPowerSmart开发软件,完成了电压控制型数字环路补偿器的设计,实现3P3Z数字补偿器的实... 针对教学环节中的难点和重点内容,基于dsPIC33CK256MP505数字信号控制器芯片,为开发新型的数字电源教具,在降压转换器的电路拓扑结构基础上,利用MplabPowerSmart开发软件,完成了电压控制型数字环路补偿器的设计,实现3P3Z数字补偿器的实时算法功能。 展开更多
关键词 数字电源 环路补偿器 数字信号控制器 教具设计
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多维关联度分析驱动的数字证据链构造方法
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作者 刘延华 欧振贵 +3 位作者 刘西蒙 陈惠文 林钟馨 张明辉 《福州大学学报(自然科学版)》 CAS 北大核心 2024年第4期404-412,共9页
提出一种基于多维关联度的数字证据链自动构造方法.首先设计一种数字证据标准化表示方法,将数字事件与其之间的关联关系进行规范化描述.然后通过对数字事件关联关系的分析,提出多维度的非因果关联度计算方法和基本证据环的构造方法,对... 提出一种基于多维关联度的数字证据链自动构造方法.首先设计一种数字证据标准化表示方法,将数字事件与其之间的关联关系进行规范化描述.然后通过对数字事件关联关系的分析,提出多维度的非因果关联度计算方法和基本证据环的构造方法,对数字事件因果关系进行深度分析.实验结果表明,所提出方法构造的数据证据链对于提升数字证据的证明力具有一定的应用意义. 展开更多
关键词 数字取证 数字证据链 证据环 关联度
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多泵切换对数字液压传动风力机工作特性影响的分析
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作者 刘增光 张本国 +3 位作者 岳大灵 李林飞 苏利强 任禄 《液压与气动》 北大核心 2024年第2期85-92,共8页
多泵数字液压传动风力机可根据风速大小使相应排量液压泵参与工作,使液压风力机在整个工作风速范围内始终保持高效。但不同排量液压泵参与工作的切换会造成风力机液压传动系统流量发生突变并产生压力冲击,影响风力机工作特性和风轮对风... 多泵数字液压传动风力机可根据风速大小使相应排量液压泵参与工作,使液压风力机在整个工作风速范围内始终保持高效。但不同排量液压泵参与工作的切换会造成风力机液压传动系统流量发生突变并产生压力冲击,影响风力机工作特性和风轮对风能的吸收。在分析多泵数字液压传动风力机工作原理的基础上,对5 MW级多泵数字液压传动风力机的方案进行设计和AMESim仿真建模;进行恒定风速和变风速条件下液压泵工作切换的仿真研究,得到多泵切换时液压风力机的风能利用系数、液压系统流量、压力等工作特性的变化规律;搭建了5 kW风能能量多泵数字液压传递半实物仿真实验平台对仿真结果进行实验验证;研究结果为多泵数字液压传动风力机风能高效利用和稳定运行提供理论依据和技术参考。 展开更多
关键词 液压风力机 数字液压传动 多泵切换 半实物仿真 工作特性
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正负脉冲电压驱动的电磁螺纹插装阀动态特性分析
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作者 刘增光 李林飞 +2 位作者 岳大灵 左秀坤 刘超 《液压与气动》 北大核心 2024年第3期82-90,共9页
提出了一种基于PWM技术的正负脉冲电压控制策略,用于提高锥阀式电磁螺纹插装阀启闭动态响应速度,使其满足数字液压技术的要求。在分析电磁螺纹插装阀结构和工作原理基础上,建立了电磁螺纹插装阀的数学模型,并在AMESim软件中搭建电磁螺... 提出了一种基于PWM技术的正负脉冲电压控制策略,用于提高锥阀式电磁螺纹插装阀启闭动态响应速度,使其满足数字液压技术的要求。在分析电磁螺纹插装阀结构和工作原理基础上,建立了电磁螺纹插装阀的数学模型,并在AMESim软件中搭建电磁螺纹插装阀及其测试系统的多物理场耦合建模,研究不同正负脉冲电压持续时间条件下电磁螺纹插装阀线圈电流、阀芯位移、电磁力的变化规律,确定了电磁螺纹插装阀响应速度最快时正负脉冲电压控制策略的最优控制参数。利用半实物仿真系统搭建SCV硬件在环测试实验台,对所提正负脉冲控制策略进行验证。实验表明,与常规电压控制策略相比,当正负脉冲电压控制策略中正负脉冲电压持续时间都为10 ms时,电磁螺纹插装阀的开启时间由30 ms缩短到13.5 ms,其关闭时间由139 ms缩短到14 ms。研究结果为电磁螺纹插装阀的高响应化和数字液压技术的发展提供参考。 展开更多
关键词 数字液压 正负脉冲电压控制 电磁螺纹插装阀 高速开关阀 硬件在环
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基于电容电压全前馈的并网逆变器高鲁棒性稳定控制策略
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作者 杨明 李玉龙 +2 位作者 杨倬 朱军 解宝 《高电压技术》 EI CAS CSCD 北大核心 2024年第9期4171-4183,I0024,共14页
虽然并网逆变器采用电容电压全前馈控制策略,能够有效抑制电网电压背景谐波对并网电流的影响。但是在弱电网工况环境下,由于锁相环、数字控制延时等因素与电网阻抗相互耦合,导致逆变器稳定较差、在阻抗交截频域中呈现弱无源性,易引发系... 虽然并网逆变器采用电容电压全前馈控制策略,能够有效抑制电网电压背景谐波对并网电流的影响。但是在弱电网工况环境下,由于锁相环、数字控制延时等因素与电网阻抗相互耦合,导致逆变器稳定较差、在阻抗交截频域中呈现弱无源性,易引发系统谐波振荡甚至失稳问题。鉴于此,该文借助无源性理论和阻抗分析方法,深度揭示了影响系统各频带阻抗特性的主导因素,进而提出了一种基于电容电压全前馈的并网逆变器高鲁棒性稳定控制策略。理论分析表明:所提控制策略不仅能有效地拓宽系统输出阻抗稳定范围,还可以保证改进后的系统输出阻抗具有较高的幅值增益。最后,通过仿真和实验验证了所提控制策略的有效性。 展开更多
关键词 弱电网 电容电压全前馈 数字控制延时 锁相环 并网逆变器 无源性理论
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数字专网的通信终端与加密组件测试系统设计
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作者 孟珞珈 郭元兴 刘皓 《计算机测量与控制》 2024年第8期78-85,共8页
为提高数字专网的通信终端与配套加密组件测试效率,降低实装测试环境的构建、运维及人力成本,开展了基于半实物仿真的测试系统设计;对通信终端与加密组件的测试需求进行了分析,提出并实现了一种模拟数字专网的通信建链流程和加密通信业... 为提高数字专网的通信终端与配套加密组件测试效率,降低实装测试环境的构建、运维及人力成本,开展了基于半实物仿真的测试系统设计;对通信终端与加密组件的测试需求进行了分析,提出并实现了一种模拟数字专网的通信建链流程和加密通信业务流程的方法;采用了通用AXIe(仪器与测试高级电信计算架构的扩展)测试平台与扩展测试仪器的架构进行系统设计,实现与不同测试对象的物理接口适配、信号调理以及报文数据交互控制,为通信终端及加密组件的加密业务成功率测试、语音质量评测以及远供工作电流测量提供自动化测试技术手段;经验证,测试系统通信链路时延<100 ns,可为通信终端提供良好的语音质量评测环境,PESQ(感知语音质量评测模型)测试≥4.20,可支持加密业务成功率指标≥99.9%的无人值守测试。 展开更多
关键词 通信终端与加密组件 测试系统 半实物仿真 模拟数字专网 AXIe平台
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一种适用于亚采样锁相环的高鲁棒性辅助锁定电路
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作者 张磊 林敏 《工业控制计算机》 2024年第10期124-125,128,共3页
当前的研究表明,基于亚采样相位检测器(Sub-Sampling Phase Detectors,SSPD)的锁相环(Phase-Locked Loop,PLL)相较传统锁相环架构可以实现显著降低的带内相位噪声。然而,在片上系统(Systems on Chip,SOCs)应用中,PLL容易受到衬底或电源... 当前的研究表明,基于亚采样相位检测器(Sub-Sampling Phase Detectors,SSPD)的锁相环(Phase-Locked Loop,PLL)相较传统锁相环架构可以实现显著降低的带内相位噪声。然而,在片上系统(Systems on Chip,SOCs)应用中,PLL容易受到衬底或电源耦合的干扰,这很可能会导致PLL失去锁定,且可能无法恢复。针对此问题,提出一种将辅助锁频环(Frequency-Locked Loop,FLL)和数字锁定检测器(Digital Lock Detector,DLD)相结合的适用于亚采样锁相环(Sub-Sampling Phase-Locked Loop,SSPLL)的高鲁棒性辅助锁定电路。仿真结果表明:与传统SSPLL相比,所提出的电路极大提升了PLL对衬底或电源干扰的鲁棒性,同时保持了其低相位噪声的优点,这对于SSPLL在大规模生产和应用中的可靠性具有重要意义。 展开更多
关键词 亚采样相位检测器 锁频环 数字锁定检测器 锁相环
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带残余频偏的软扩频信号伪码序列盲估计
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作者 张天骐 张慧芝 +1 位作者 罗庆予 方蓉 《系统工程与电子技术》 EI CSCD 北大核心 2024年第10期3586-3593,共8页
针对带残余频偏的软扩频信号伪码序列盲估计难的问题,提出一种奇异值分解(singular value decomposition,SVD)结合全数字锁相环(digital phase locked loop,DPLL)的方法。所提方法首先对待处理信号通过不重叠分段生成数据矩阵,每段信号... 针对带残余频偏的软扩频信号伪码序列盲估计难的问题,提出一种奇异值分解(singular value decomposition,SVD)结合全数字锁相环(digital phase locked loop,DPLL)的方法。所提方法首先对待处理信号通过不重叠分段生成数据矩阵,每段信号长度为一倍伪码周期;然后利用其自相关矩阵的右上角元素估计失步点进行同步,并且在重新计算自相关矩阵后根据较大特征值个数估计进制数;最后通过多次快速SVD算法结合DPLL最终实现伪码序列的盲估计。仿真结果显示,所提方法在低信噪比条件下可以有效估计出带残余频偏的软扩频信号的伪码序列,并且性能优于其他对比方法。 展开更多
关键词 软扩频信号 盲估计 残余频偏 奇异值分解 全数字锁相环
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实物在环实时仿真教学法研究
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作者 刘丽 《高教学刊》 2024年第2期106-110,共5页
新工科背景下,为培养学生创新实践能力,建设国家级一流本科课程,提出了一种新型的适用于电子技术基础课程的教学方法——实物在环实时仿真教学法,应用于北航数字电子技术基础课程。通过口袋仪器和实际硬件进行数字电路设计,可解决虚拟... 新工科背景下,为培养学生创新实践能力,建设国家级一流本科课程,提出了一种新型的适用于电子技术基础课程的教学方法——实物在环实时仿真教学法,应用于北航数字电子技术基础课程。通过口袋仪器和实际硬件进行数字电路设计,可解决虚拟仿真的真实性问题,培养学生解决复杂工程问题的能力;通过虚拟仪器展示波形,使知识难点可视化,有助于学生更快、更深刻理解。实践表明,这种方法取得了良好的教学效果,提高了教学质量。通过该教学方法学生获得了更丰富的学习体验,培养了创新实践能力。 展开更多
关键词 实物在环仿真 口袋仪器 数字电路设计 虚拟仪器 知识难点可视化
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