一种前后台结合的Pipelined ADC校准技术

针对Pipelined模数转换器(ADC)中采样电容失配和运放增益误差带来的非线性问题,提出了一种前后台结合的Pipelined ADC校准技术。前台校准技术通过对ADC量化结果的余量分析,补偿相应流水级的量化结果,后台校准技术基于伪随机(PN)注入的方式,利用PN的统计特性校准增益误差。本校准技术在系统级建模和RTL级电路设计的基础上,实现了现场可编程门阵列(FPGA)验证并成功流片。测试结果显示,在1 GS/s采样速率下,校准精度为14 bit的Pipelined ADC的有效位数从9.30 bit提高到9.99 bit,信噪比提高约4 dB,无杂散动态范围提高9.5 dB,积分非线性(INL)降低约10 LSB。

Study on the Technology of Supplying Water Safely by Long-Distance Pipeline

The extensively built long-distance water transmission pipelines have become the main water sources for urban areas. To ensure the reliability and safety of the water supply, from the viewpoint of overall management, it would be necessary to establish a system of information management for the pipeline. The monitoring, calculating and analyzing functions of the system serve to give controlling instructions and safe operating rules to the automatic equipment and technician, making sure the resistance coefficient distribution along the pipeline is reasonable; the hydraulic state transition is smooth when operating conditions change or water supply accidents occur, avoiding the damage of water hammer. This paper covered the composition structures of the information management system of long-distance water transmission pipelines and the functions of the subsystems, and finally elaborated on the approaches and steps of building a mathematics model for the analysis of dynamic hydraulic status.

Criterions and Measures of Route Selection of Shallowly Embedded Long-Distance Oil and Gas Pipeline in Mountain Areas

According to the engineering investigation of long-distance oil and gas pipelines, the criterions and measures of route selection are drawn as follows： the flat landform is the first choice in route alignment. The foot of mountain is the first choice when the route passes by the valley. The route should pass by but the shady and deposited slope and not in sunny and erosive slope as possible as it can. The pipeline should be vertical to contour climbing and descending the mountain except steep slope. Tunnel can be used in crossing foothill. Perpendicularly traversing the river is better than beveling; the worst choice is to put the pipeline along the river. Bypass is the best choice in karsts area. The order of route selection should be pre-choosing, investigation, optimization and adjustment.

THE RISK ASSESSMENT OF THE LONG-DISTANCE OILPIPELINE ENGINEERING

The oilfield construction and long-distance oil pipeline engineering has been developed extensively in China. The risk assessment of oil industry will, however, be an important objective to cope with the development of oil industry , The risk assessment of oil industry has many subjects worthy to be studied.The major purpose of the paper is to research the risk cases of long-distance oil pipeline engineering in Ganshu and Shaanxi provinces.

A FAST FOREGROUND DIGITAL CALIBRATION TECHNIQUE FOR PIPELINED ADC

Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the analysis of error sources which influence the resolution of pipelined ADCs. This method estimates the gain error of the ADC prototype quickly and calibrates the ADC simultaneously in the operation time. Finally, a 10 bit, 100 Ms/s pipelined ADC is implemented and calibrated. The simulation results show that the digital calibration technique has its efficiency with fewer operation cycles.

A 1.5 bit/s Pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch

A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.

PIPELINED多值A/D转换器

通过对多值ADC数学表示的分析，指出了多值ADC具有更高的信息密度。本文结合数字电路的开关信号理论，设计了Pipelined三值ADC。该ADC在保证较高转换速度的同时具有相对简单的电路结构。

一种采用pipeline-ΔΣ时间-数字转换器的全数字锁相环

提出了一种采用pipeline-ΔΣ时间-数字转换器的全数字锁相环。提出的pipeline-ΔΣ时间-数字转换器采用脉冲链结构的时间放大器实现了两级时间量化以及1.6ps的高分辨率。其中,MASH1-1-1结构的ΔΣ调制器实现了三阶噪声整形的效果。该全数字锁相环电路采用0.13μm CMOS工艺进行了流片,测试结果显示:芯片总功耗为12mW,带内和带外相位噪声分别为-91dBc/Hz@10kHz和-128dBc/Hz@1MHz,RMS抖动和峰峰抖动值分别为2.9ps和21.5ps。

Water hammer protection for diversion systems in front of pumps in long-distance water supply projects

For a water supply system with long-distance diversion pipelines, in addition to the water hammer problems that occur beyond pumps, the safety of the water diversion pipeline in front of pumps also deserves attention. In this study, a water hammer protection scheme combined with an overflow surge tank and a regulating valve was developed. A mathematical model of the overflow surge tank was developed, and an analytical formula for the height of the overflow surge tank was derived. Furthermore, a practical water supply project was used to evaluate the feasibility of the combined protection scheme and analyze the sensitivity of valve regulation rules. The results showed that the combined protection scheme effectively reduced the height of the surge tank, lessened the difficulties related to construction, and reduced the necessary financial investment for the project. The two-stage closing rule articulated as fast first and then slow could minimize the overflow volume of the surge tank when the power failure occurred, while the two-stage opening rule articulated as slow first and then fast could be more conducive to the safety of the water supply system when the pump started up.

Relationship between ponding and topographic factors along the China-Russia Crude Oil Pipeline in permafrost regions

The original landform along the China Russia Crude Oil Pipeline(CRCOP,line 2)was disturbed during installation of pavement for the pipeline.Forest and vegetation coverage is dense,and runoff develops along the pipe.Since the opera tion of the CRCOP(line 2)began in 2018,ponding has appeared on both sides of the pipeline.If there is no drainage,ponding can hardly dissipate,due to the low permeability of the permafrost layer.With the supply of surface flow and the transportation of oil at positive temperatures,ponding promotes an increase in temperature and changes the boundary ther mal conditions of the pipeline.Meanwhile,when the ponding freezes and thaws,frost heave threatens operational safety of the pipeline.Furthermore,the ponding can affect the thermal condition of line 1.In this paper,the distribution of pond ing along the CRCOP was obtained by field investigation.The type and cause of ponding were summarized,and the catch ment and stream order were extracted by the Digital Elevation Model(DEM).According to the statistical results in attri butes for topographic factors,it is known that ponding along the pipeline is relative to elevation,slope,aspect,and the Topographic Wetness Index(TWI).Water easily accumulates at altitudes of 300450 m,slopes within 3°5°,aspect in the northeast or south,TWI within 1316,flow direction in north east south,and flow length within 90150 km.This paper proposes a theoretical basis for the cause and characteristics of ponding along the pipeline.

DATA BYPASSING ARCHITECTURE AND CIRCUIT DESIGN FOR 32-BIT DIGITAL SIGNAL PROCESSOR

This paper presents a design method of ByPassing Unit(BPU) in 32-bit Digital Signal Processor(DSP)-MD32. MD32 is realized in 0,18μm technology, 1.8V and 200 MHz working clock. It focuses on the Reduced Instruction Set Computer(RISC) architecture and DSP computation capability thoroughly, extends DSP with various addressing modes in a customized DSP pipeline stage architecture. The paper also discusses the architecture and circuit design of bypassing logic to fit MD32 architecture. The parallel execution of BPU with instruction decode in architecture level is applied to reduce time delay. The optimization of circuit that serial select with priority is analyzed in detail, and the result shows that about half of time delay is reduced after this optimization. Examples show that BPU is useful for improving the DSP's performance.The forwarding logic in MD32 realizes 8 data channels feedback and meets the working clock limit.

The CMEKF Method for Sub-Sea Pipeline Monitoring and Leak Detection

A practical approach is discussed for sub-sea pipeline monitoring and leak detection based on the real time transient model . The characteristic method of transient simulation is coupled with the Extended Kalman Filter to estimate the system state where the only observed data are inlet and outlet flow rate and pressure. Because EKF has a time variant track under the non-stationary stochastic process with additive Gaussian noise, the high sensitivity of RTTM to non-stationary operating condition is reduced. A leak location recursion estimation formula is presented based on the real time observed data. The results of 27 groups of test data indicate that the procedure presented is sensitive to a wide range of detectable leak sizes and has a low average relative error of leak location .

A Novel Power Optimization Method by Minimum Comparator Number Algorithm for Pipeline ADCs

The effects of stage numbers on power dissipation of pipeline analog-to-digital converter （ADC） are studied and a novel design method aiming for power optimization is presented. In this method, a minimum comparator number algorithm （MCNA） is first introduced, and then the optimum distribution of resolutions through pipeline ADC stages is deduced by MCNA. Based on the optimum stage-resolution distribution, an optimization method is established, which examines the precise function between ADC power and stage resolutions with a parameter of power ratio （Rp）. For 10-bit pipeline ADC with scaling down technology, the simulation results by using MATLAB CAD tools show that an eight-stage topology with 1-bit RSD correction achieves the power optimization indicated by the power reduction ratio.

FPGA Implementation of Wave Pipelining CORDIC Algorithms

The implementation of the coordinate rotational digital computer （CORDIC） algorithm with wave pipelining technique on field programmable gate array （FPGA） is described. All data in FPGA-based wave pipelining pass through a number of logic gates, in the same way that all data pass through the same number of registers in a conventional pipeline. Moreover, all paths are routed using identical routing resources. The manual placement, timing driven routing and timing analyzing techniques are applied to optimize the layout for achieving good path balance. Experimental results show that a 256-LUT logic depth circuit mapped on XC4VLX15-12 runs as high as 330 MHz, whichis a little lower than the speed of 336 MHz based on the conventional 16-stage pipelining in the same chip. The latency of the wave pipelining circuit is 30.3 ns, which is 36.4% shorter than the latency of 16-stage conventional pipelining circuit.

A 12-bit 250-MS/s Charge-Domain Pipelined Analog-to-Digital Converter with Feed-Forward Common-Mode Charge Control

A feed-forward Common-Mode （CM） charge control circuit for a high-speed Charge-Domain （CO） pipelined Analog-to-Digital Converter （ADC） is presented herein. This study aims at solving the problem whereby the precision of CD pipelined ADCs is restricted by the variation in input CM charge, which can compensate for CM charge errors caused by a variation in CM charge input in real time. Based on the feed-forward CM charge control circuit, a 12-bit 250-MS/s CD pipelined ADC is designed and realized using a 1P6M 0.18-μm CMOS process. The ADC achieved a Spurious Free Dynamic Range （SFDR） of 78.1 dB and a Signal-to-Noise-and-Distortion Ratio （SNDR） of 64.6 dB for a 20.1-MHz input; a SFDR of 74.9 dB and SNDR of 62.0 dB were achieved for a 239.9-MHz input at full sampling rate. The variation in signal-to-noise ratio was less than 3 dB over a 0-1.2 V input CM voltage range. The power consumption of the prototype ADC is only 85 mW at 1.8 V supply, and it occupies an active die area of 2.24 mm^2.

A 12-bit 100 MS/s pipelined ADC with digital background calibration

This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC） with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter （MDAC） while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18μm CMOS process, occupies an active area of 2.3 × 1.6 mm^2, and consumes 205 mW at 1.8 V.

A new structure of substage in pipelined analog-to-digital converters

The article presents a new （1＋1）-bit/stage structure for pipelined analog-to-digital converters （ADC）. When the input analog signal of the structure exceeds the converting range of the whole ADC, the signal can still be converted precisely and the output residue voltage of the structure will be in the converting range of the ADC. The structure is used in a 12-bit 40 MS/s pipelined ADC to test its function. The testing results show that the structure has right function and can correct the transition error induced by offset of comparators＇ decision levels. The ADC implemented in Semiconductor Manufactory International Corporation （SMIC） 0.18 μm CMOS process consumes 210 mW and occupies a chip area of 3.2×3.7 mm2.

A robust and simple two-mode digital calibration technique for pipelined ADC

This paper presents a two-mode digital calibration technique for pipelined analog-to-digital converters （ADC）.The proposed calibration eliminates the errors of residual difference voltage induced by capacitor mismatch of pseudorandom（PN） sequence injection capacitors at the ADC initialization,while applies digital background calibration to continuously compensate the interstage gain errors in ADC normal operation.The presented technique not only reduces the complexity of analog circuit by eliminating the implementation of PN sequence with accurate amplitude in analog domain,but also improves the performance of digital background calibration by minimizing the sensitivity of calibration accuracy to sub-ADC errors.The use of opamps with low DC gains in normal operation makes the proposed design more compatible with future nanometer CMOS technology.The prototype of a 12-bit 40-MS/s pipelined ADC with the two-mode digital calibration is implemented in 0.18-μm CMOS process.Adopting a simple telescopic opamp with a DC gain of 58-dB in the first stage,the measured SFDR and SNDR within the first Nyquist zone reach 80-dB and 66-dB,respectively.With the calibration,the maximum integral nonlinearity （INL） of the ADC reduces from 4.75-LSB to 0.65-LSB,while the ADC core consumes 82-mW at 3.3-V power supply.

基于数字化的核级管道系统设计与力学分析协同技术研究

为了解决核级管道系统设计与力学分析协同问题,通过数字化技术及程序开发打通管道力学分析过程中的数据链路与接口传递,包括:开发设计管道力学分析PEPS与三维布置软件Creo的数据模型接口;建立管道力学分析所需数据的参数池,例如材料属性、管道规格、阀门参数及管道载荷数据等;设计开发平台主程序,实现管道分析模型自动生成,调用PEPS软件求解器计算;创建管道力学分析报告模板,计算结果报告自动生成等。通过工程应用,数字化技术的运用可实现工程分析数据的集成共享与高效利用,提升管道系统力学分析过程的数据协同能力以及质量。

基于时钟抖动流水线结构的高效率真随机数发生器

现代加密系统对密钥随机性的需求不断增加。使用时序抖动、热噪声、亚稳态等作为熵源的真随机数发生器,因其可以提供高质量的随机性成为该领域的研究热点。因此,提出一种可配置、轻量级、高效率的真随机数发生器。该发生器使用基于随机数学模型的设计方法,由差分构架的两级时钟抖动流水线组成。第一级流水线中两个环形振荡器在规定时间内累积抖动,第二级流水线利用近似相同的两个环形振荡器的微小周期差构建时间数字转换器,对第一级输出的高斯抖动进行量化,通过数字化模块输出随机比特。在时间数字转换器运行过程中,第一级流水线已经重新启动累积下一个阶段的抖动,减少了空闲时间,提高了真随机数的质量和效率。在Xilinx Atrix-7平台进行了验证,该结构的硬件资源仅消耗了25个LUTs和13个DFFs,获得高达32.55 Mb/s的吞吐量。