EXACT ANALYSIS OF SPURIOUS SIGNALS IN DIRECT DIGITAL FREQUENCY SYNTHESIZERS DUE TO AMPLITUDE QUANTIZATION

Amplitude quantization is one of the main sources of spurious noise frequencies in Direct Digital Frequency Synthesizers (DDFSs), which affect their application to many wireless telecommu- nication systems. In this paper, two different kinds of spurious signals due to amplitude quantization in DDFSs are exactly formulated in the time domain and detailedly compared in the frequency do- main, and the effects of the DDFS parameter variations on the spurious performance are thoroughly studied. Then the spectral properties and power levels of the amplitude-quantization spurs in the absence of phase-accumulator truncation are emphatically analyzed by waveform estimation and computer simulation, and several important conclusions are derived which can provide theoretical support for parameter choice and spurious performance evaluation in the application of DDFSs.

Low spurious noise frequency synthesis based on a DDS-driven wideband PLL architecture

An S-band frequency synthesizer for a stepped-frequency radar is presented. This frequen- cy synthesizer is based on a direct digital synthesizer （ DDS ） -driven wideband phase-locked loop （PLL） architecture which can achieve low spurious noise and rapid frequency hopping simultaneous- ly. The mechanism of introducing high level spurs by the images of DDS digital to analog convertor （DAC） output is analyzed. A novel DDS frequency planning method is proposed to ensure low col- ored noise within the entire bandwidth. The designed output frequency range is 3. 765 -4. 085 GHz, and the step size is 5 MHz with frequency agility of less than 1 μs. Measured results demonstrate that the average spurious free dynamic range （SFDR） is about 64 dBc in a 320 MHz bandwidth.

Measurement of soil electrical conductivity based on direct digital synthesizer(DDS)and digital oscilloscope

A soil electrical conductivity(EC)measurement system based on direct digital synthesizer(DDS)and digital oscilloscope was developed.The system took the“current-voltage four-electrode method”as the design principal and adopted a six-pin structure of the probe,two center pins to measure the soil EC in shallow layer,two outside pins to measure the soil EC in deep layer,and two middle pins for inputting the driving current.A signal generating circuit using DDS technology was adopted to generate sine signals,which was connected with the two middle pins.A digital oscilloscope was used to record and store the two soil output signals with noises in microseconds,which were from the two center pins and two outside pins,respectively.Then a digital bandpass filter was used to filter the soil output signals recorded by the digital oscilloscope.Compared with the traditional analog filter circuit,the digital filter could filter out the noises of all frequency except for the frequency of the excitation source.It could improve the effect of filtering and the accuracy of the soil EC measurement system.The DDS circuit could provide more stable sine signals with larger amplitudes.The use of digital oscilloscope enables us to analyze the soil output signals in microseconds and measure the soil EC more accurately.The new soil EC measurement system based on DDS and digital oscilloscope can provide a new effective tool for soil sensing in precision agriculture.

A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC

This paper presents a high speed ROM-less direct digital frequency synthesizer （DDFS） which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic （CML） is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm^2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0℃.

A high-performance MUX-direct digital frequency synthesizer with quarter ROMs

This paper presents a detailed description of a high-performance direct digital frequency synthesizer （DDFS） using optimized quarter ROMs. To improve the working frequency and spectral purity, an original quarter ROMs structure in 0.13 μm CMOS is brought forward and implemented. The working frequency is increased by 40% compared with Yuan Ling＇s methodIll of implementing a segmented DAC based DDFS. It has been implemented in 0.13 μm CMOS technology. The DDFS has a resolution of 10 bits with a measured SFDR 54 dBc. Its maximum operating frequency is 1.2 GHz by using six pipelining stages. Analytical investigation of improving spectral performances by using dual-slope approximation and pipeline is also presented.

A high speed direct digital frequency synthesizer based on multi-channel structure

This paper presents a direct digital frequency synthesizer （DDFS） for high speed application based on multi-channel structure. This DDFS has phase resolution of 32 bits and magnitude resolution of 12 bits. In order to ensure the high speed and high resolution at the same time, the multi-channel sampling technique is used and a 12 bits linear digital-to-analog converter is implemented. The chip is fabricated in TSMC 130 nm CMOS technology with active area of 0.89 x 0.98 mm2 and total power consumption of 300 mW at a single 1.2 V supply voltage. The maximum operating speed is up to 2.0 GHz at room temperature.

Audio Video Compression Stream Synthesis and Implementation

Multiplex of digital streams is one of the key technologies in audio-video communication, and determines audio-video quality. A design scheme for an MPEG2 compliant digital television system including audio-video encoding and multiplexing was implemented. The principles and elements of system layer stream synthesis were analyzed. The key technologies of video and audio PES packetization were discussed, such as stream structure, scheduling matching, audio-video synchronization, data flow and buffering. DSP and FPGA are combined to construct header information and packet structure. The substitution of traditional RAM or PLD results in high operational efficiency and saves memory space. A scheduling algorithm was introduced for PES coding, using the monitor information of PES buffers. DTS is generated by multiplexer to guarantee synchronization. The system is not only simple but also stable, and maintains synchronization constraints of the standard. It supports both analogy and digital audio-video source input, and provides real-time MPEG2 compliant TS/PS output. It has perfect performance and meets the national broadcasting requirements.

A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications

A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications is successfully realized by the 130 nm CMOS process. A series of novel methods are proposed in this paper.Two band DCOs with high frequency resolution are utilized to cover the frequency band of interest, which is as wide as 2.5 to 5 GHz. An overflow counter is proposed to prevent the ＂pulse-swallowing＂ phenomenon so as to significantly reduce the locking time. A NTW-clamp digital module is also proposed to prevent the overflow of the loop control word. A modified programmable divider is presented to prevent the failure operation at the boundary.The measurement results show that the output frequency range of this frequency synthesizer is 0.8–4.2 GHz. The locking time achieves a reduction of 84% at 2.68 GHz. The best in-band and out-band phase noise performances have reached –100 d Bc/Hz, and –125 d Bc/Hz respectively. The lowest reference spur is –58 d Bc.

基于STM32的信号分离电路设计与实现

文章提出了一种有效分离并重构信号的数字化方案。信号A和信号B通过加法器叠加成信号C,对信号C进行快速傅里叶变换,再通过直接数字合成(Direct Digital Synthesizer,DDS)模块分别输出重构信号A′和重构信号B′。测试结果表明:当输入信号为1时,V PP的正弦波或者三角波频率在10~100 kHz。所提方案能够有效分离出2路重构信号,重构信号无失真、无漂移,能够调节2路信号相位差。

基于改进型RBF神经网络的直接数字频率合成器设计

提出了一种基于改进型径向基函数(Radial basis function,RBF)神经网络的高性能直接数字频率合成器,相比于传统的直接数字频率合成器避免了相位截断误差并降低了资源消耗。为了进一步提高RBF神经网络的训练效率及稳定性,提出一种改进型的RBF神经网络训练算法。该算法在粗调阶段,利用K-means++算法快速确定初始激活函数中心,使激活函数中心分布更加合理;在细调阶段则采用L-BFGS-B算法,对粗调阶段得到的最佳中心进行精细调整,进一步降低输出误差。通用FPGA平台的实验结果表明,基于改进型RBF神经网络的直接数字频率合成器当输出时钟频率为1.53 MHz时,无杂散动态范围为85.26 dB,相位噪声为-90.50 dBc/Hz@100 kHz,且无需占用额外ROM资源。

UAT2数据链发射机编码及调制技术

为应对低空空域飞行器数量的增加及航空产业对未来城市空中交通(UAM)飞行器的监视跟踪需求,文章对UAT2数据链发射机的编码与调制技术进行研究:搭建UAT2数据链发射机系统结构,针对UAM飞行器监视需求,提出可寻址数据上行链路通信编码及飞行器健康状况监测下行链路编码规则算法,旨在全面覆盖UAM的安全运行需求;开发一种UAT2报文的轻量高速化RS编码算法,以减少执行时间和内存占用;基于直接数字频率合成DDS技术,实现连续相位频移键控CPFSK调制,符合UAT2数据链信号要求,确保了频谱能量的集中分布。关键编码和调制技术经过测试分析与性能评估,能够有效适用于UAT2数据链发射机。

便携式生物电阻抗测量系统的设计与应用

生物电阻抗可用于人体成分测量,具有重要的临床意义与应用价值,现阶段的生物电阻抗测量设备仍存在成本高昂、设备笨重的问题。因此,提出了一种便携式生物电阻抗测量系统,其由控制电路、电流发射电路与阻抗测量电路组成,通过微控制器STC12C5A60S2对直接数字频率合成器AD9833、鉴相器AD8302等微型模块的有效控制,实现对不同频率下人体生物电阻抗的精准稳定测量。研究结果表明,该系统在设计复杂度与实现成本远低于商用人体生物电阻抗仪的前提下,实现了与之类似的测量精确度,有望为生物电阻抗测量装置的小型化、便携化、低成本化发展提供新的思路。

基于FPGA的阵列信号发生方法

使用数字发生的阵列信号,可以快速方便地开展阵列信号处理系统的测试和验证。为此设计了一种基于现场可编程门阵列(FPGA)的阵列信号发生方法,通过小数延时和整数延时相结合的方式,实现点频和线性调频的阵列信号发生。

AD9850 DDS芯片信号源的研制

直接数字合成 ( Direct Digital Synthesize,DDS)是一种重要的频率合成技术 ,具有分辨率高 ,频率变换快等优点。阐述了性能价格比较高的 AD985 0直接数字频率合成器芯片的基本原理和性能特点 ,以及用其研制的 0～ 30 MHz信号源。

基于FPGA的DDS信号发生器设计

设计了一种可灵活在线调节的直接数字频率合成信号发生器,首先利用现场可编程门阵列生成各种频率、波形的信号数据,再采用LTC1821实现D/A转换,最后通过选择性滤波和功率放大电路实现信号输出,幅值范围0～10V,频率范围1Hz～100kHz,波形可设为三角波、矩形波、正弦波、锯齿波;实际测试验证了信号发生器的准确性和有效性。

DDS技术在数字激光相位测距仪中的应用

本文介绍了直接数字合成(DDS)技术在激光相位测距仪中的应用。使用该技术研制的数字激光相位测距仪具有操作简便、携带方便、性能可靠的特点,测相精度优于千分之一。

采用DDS频率合成的虚拟信号发生器研究

根据直接数字频率合成(DDS)原理,结合虚拟仪器平台提供的丰富软硬件资源,利用软件分段计算产生波形数据,通过数据采集卡(PC-DAQ)输出,输出信号频率分辨率高;频率跳变速度快;频谱纯度高.文中分析了虚拟信号发生器的各项性能指标,比较了其输出频谱与传统DDS输出的差异,最后给出了实验结果.该信号发生器已成功用作虚拟压电参数测量系统中的信号源.

基于FPGA的直接数字频率合成器的设计

本文介绍了直接数字频率合成器(DDS)的基本组成及设计原理,给出了基于FPGA的具体设计方案及编程实现方法。仿真结果表明,该设计简单合理,使用灵活方便,具有良好的性价比。

基于DSP的直接数字频率合成器的研究和实现

作为微机继电保护测试仪核心部件之一,数字信号发生器的品质直接影响测试系统的整体性能。本文介绍了基于的高性能DSP芯片TMS320F2812实现直接数字频率合成器的工作原理、设计思想和软硬件结构;并提出一种优化的DDS实现方法,通过试验证明可进一步提高数字信号发生器的实时性与稳定性。该系统在一种新型微机继电保护测试仪中得到应用;实际应用表明:该类型测试仪可完成各类型的继保测试实验。

单片直接数字频率合成器产品发展综述

综合论述了单片直接数字频率合成器(DDS)产品的现状、应用范围以及发展趋势。以目前国际上单片DDS产品公开发布的产品介绍资料为基础,根据DDS产品的性能和功能进行统计和分析,得到关于DDS产品的一些有用的结论。以DDS的不同功能特点为依据,分别介绍了其在不同领域的应用情况,最后给出单片DDS产品的发展趋势预测。