The stable operation of first and second order Zero Crossing Digital Phase Locked Loop (ZCDPLL) is extended by using a Fixed Point Iteration (FPI) method with relaxation. The non-linear components of ZCDPLL such as sa...The stable operation of first and second order Zero Crossing Digital Phase Locked Loop (ZCDPLL) is extended by using a Fixed Point Iteration (FPI) method with relaxation. The non-linear components of ZCDPLL such as sampler phase detector and Digital Controlled Oscillator (DCO) lead to unstable and chaotic operation when the filter gains are high. FPI will be used to stabilize the chaotic operation and consequently extend the lock range of the loop. The proposed stabilized loop can work in higher filter gains which are needed for faster signal acquisition.展开更多
This paper presents an approach of singular value de- composition plus digital phase lock loop to solve the difficult problem of blind pseudo-noise （PN） sequence estimation in low signal to noise ratios （SNR） dire...This paper presents an approach of singular value de- composition plus digital phase lock loop to solve the difficult problem of blind pseudo-noise （PN） sequence estimation in low signal to noise ratios （SNR） direct sequence spread spectrum （DS-SS） signals with residual carrier. This approach needs some given parameters, such as the period and code rate of PN sequence. The received signal is firstly sampled and divided into non-overlapping signal vectors according to a temporal window, whose duration is two periods of PN sequence. An autocorrelation matrix is then computed and accumulated by those signal vectors one by one. The PN sequence with residual carrier can be estimated by the principal eigenvector of the autocorrelation matrix. Further more, a digital phase lock loop is used to process the estimated PN sequence, it estimates and tracks the residual carrier and removes the residual carrier in the end. Theory analysis and computer simulation results show that this approach can effectively realize the PN sequence blind estimation from the input DS-SS signals with residual carrier in lower SNR.展开更多
This paper presents the architectures, algorithms, and implementation considerations of the digital phase locked loop (DPLL) used for burst-mode packet DS-CDMA receivers. As we know, carrier offset is a rather challen...This paper presents the architectures, algorithms, and implementation considerations of the digital phase locked loop (DPLL) used for burst-mode packet DS-CDMA receivers. As we know, carrier offset is a rather challenging problem in CDMA system. According to different applications, different DPLL forms should be adopted to correct different maximum carrier offset in CDMA systems. One classical DPLL and two novel DPLL forms are discussed in the paper. The acquisition range of carrier offset can be widened by using the two novel DPLL forms without any performance degradation such as longer acquisition time or larger variance of the phase error. The maximum acquisition range is 1/(4T), where T is the symbol period. The design can be implemented by FPGA directly.展开更多
文摘The stable operation of first and second order Zero Crossing Digital Phase Locked Loop (ZCDPLL) is extended by using a Fixed Point Iteration (FPI) method with relaxation. The non-linear components of ZCDPLL such as sampler phase detector and Digital Controlled Oscillator (DCO) lead to unstable and chaotic operation when the filter gains are high. FPI will be used to stabilize the chaotic operation and consequently extend the lock range of the loop. The proposed stabilized loop can work in higher filter gains which are needed for faster signal acquisition.
基金supported by the National Natural Science Foundation of China (10776040 60602057)+4 种基金Program for New Century Excellent Talents in University (NCET)the Project of Key Laboratory of Signal and Information Processing of Chongqing (CSTC2009CA2003)the Natural Science Foundation of Chongqing Science and Technology Commission (CSTC2009BB2287)the Natural Science Foundation of Chongqing Municipal Education Commission (KJ060509 KJ080517)
文摘This paper presents an approach of singular value de- composition plus digital phase lock loop to solve the difficult problem of blind pseudo-noise （PN） sequence estimation in low signal to noise ratios （SNR） direct sequence spread spectrum （DS-SS） signals with residual carrier. This approach needs some given parameters, such as the period and code rate of PN sequence. The received signal is firstly sampled and divided into non-overlapping signal vectors according to a temporal window, whose duration is two periods of PN sequence. An autocorrelation matrix is then computed and accumulated by those signal vectors one by one. The PN sequence with residual carrier can be estimated by the principal eigenvector of the autocorrelation matrix. Further more, a digital phase lock loop is used to process the estimated PN sequence, it estimates and tracks the residual carrier and removes the residual carrier in the end. Theory analysis and computer simulation results show that this approach can effectively realize the PN sequence blind estimation from the input DS-SS signals with residual carrier in lower SNR.
文摘This paper presents the architectures, algorithms, and implementation considerations of the digital phase locked loop (DPLL) used for burst-mode packet DS-CDMA receivers. As we know, carrier offset is a rather challenging problem in CDMA system. According to different applications, different DPLL forms should be adopted to correct different maximum carrier offset in CDMA systems. One classical DPLL and two novel DPLL forms are discussed in the paper. The acquisition range of carrier offset can be widened by using the two novel DPLL forms without any performance degradation such as longer acquisition time or larger variance of the phase error. The maximum acquisition range is 1/(4T), where T is the symbol period. The design can be implemented by FPGA directly.
