CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a bri...CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.展开更多
In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system (MEMS) gyroscope are analyzed in principle. A novel drive circuit for...In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system (MEMS) gyroscope are analyzed in principle. A novel drive circuit for the MEMS gyroscope in digital closed-loop control is proposed, which utilizes a digital phase-locked loop (PLL) in frequency control and an automatic gain control (AGC) method in amplitude control. A digital processing circuit with a field programmable gate array (FPGA) is designed and the experiments are carried out. The results indicate that when the temperature changes, the drive frequency can automatically track the resonant frequency of gyroscope in drive mode and that of the oscillating amplitude holds at a set value. And at room temperature, the relative deviation of the drive frequency is 0.624 ×10^-6 and the oscillating amplitude is 8.0 ×10^-6, which are 0. 094% and 18. 39% of the analog control program, respectively. Therefore, the control solution of the digital PLL in frequency and the AGC in amplitude is feasible.展开更多
We propose a novel hybrid phase-locked loop (PLL) architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a...We propose a novel hybrid phase-locked loop (PLL) architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator (VCO) and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor (CMOS) process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.展开更多
This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objec...This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power,jitter and area.An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analyt-ically and benchmarked with respect to their figure-of-merit(FoM).The paper also summarizes the key concerns on the selection of dif-ferent circuit techniques to optimize the clock performance under dif-ferent scenarios.展开更多
Chirp超宽带具有峰值平均功率比(peak to average power ratio,PAPR)接近为1、测距定位能力强等优势,能够有效解决传统的超宽带技术存在的PAPR过大、传输距离短等问题,设计并产生Chirp超宽带信号是实现该通信系统的关键技术之一。提出...Chirp超宽带具有峰值平均功率比(peak to average power ratio,PAPR)接近为1、测距定位能力强等优势,能够有效解决传统的超宽带技术存在的PAPR过大、传输距离短等问题,设计并产生Chirp超宽带信号是实现该通信系统的关键技术之一。提出了一种高性能Chirp超宽带信号源方案,通过采用现场可编程门阵列(field-programma-ble gate array,FPGA)控制直接数字频率合成(direct digital synthesis,DDS)芯片AD9956产生低频Chirp信号,并结合锁相环(phase locked loop,PLL)技术实现带宽扩展,从而获得Chirp超宽带信号。实验表明,所设计的Chirp超宽带信号源具有结构简单、可编程、可扩展、性能好及实用性强等优点。展开更多
A digital phase-locked loop (DPLL) based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works...A digital phase-locked loop (DPLL) based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works from 60 to 600MHz at a supply voltage of 1.8V. It also features a fraetional-N synthesizer with digital 2nd-order sigma-delta noise shaping, which can achieve a short lock time,a high frequency resolution,and an improved phase-noise spectrum. The DPLL has been implemented in SMIC 0. 18μm 1.8V 1P6M CMOS technology. The peak-to-peak jitter is less than 0. 8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider.展开更多
Voltage source converter based high-voltage direct current(VSC-HVDC)transmission technology has been extensively employed in power systems with a high penetration of renewable energy resources.However,connecting a vol...Voltage source converter based high-voltage direct current(VSC-HVDC)transmission technology has been extensively employed in power systems with a high penetration of renewable energy resources.However,connecting a voltage source converter(VSC)to an AC weak grid may cause the converter system to become unstable.In this paper,a phase-shift phaselocked loop(PS-PLL)is proposed wherein a back electromotive force(BEMF)observer is added to the conventional phaselocked loop(PLL).The BEMF observer is used to observe the voltage of the infinite grid in the stationaryαβframe,which avoids the problem of inaccurate observations of the grid voltage in the dq frame that are caused by the output phase angle errors of the PLL.The VSC using the PS-PLL can operate as if it is facing a strong grid,thus enhancing the stability of the VSC-HVDC system.The proposed PS-PLL only needs to be properly modified on the basis of a traditional PLL,which makes it easy to implement.In addition,because it is difficult to obtain the exact impedance of the grid,the influence of shortcircuit ratio(SCR)estimation errors on the performance of the PS-PLL is also studied.The effectiveness of the proposed PSPLL is verified by the small-signal stability analysis and timedomain simulation.展开更多
In renewable power generation systems,ensuring the synchronization of the inverter and the power grid is crucial for the stable operation of grid-connected inverters.Nowadays,the phase-locked loop(PLL)technology has b...In renewable power generation systems,ensuring the synchronization of the inverter and the power grid is crucial for the stable operation of grid-connected inverters.Nowadays,the phase-locked loop(PLL)technology has become a widely used grid synchronization method because of its simple implementation and robustness under various grid conditions.Even though a lot of PLLs have been proposed,an overview and comparative analysis of multiple PLLs can be helpful for practical applications.In addition,the weak grid condition is a great challenge for the system.Therefore,this study first presents an overview of the existing PLLs together with their general structures and basic working principles.Depending on the implementation of the phase detector,the PLL can be divided into three categories:power-based PLL(pPLL),orthogonal-signalgenerator-based PLL(OSG-PLL)and adaptive-filter-based PLL(AF-PLL).Then,from the above classification,seven typical single-phase PLLs are selected for further study.Finally,some test results are given,and a comprehensive evaluation of the selected PLLs under different grid conditions is conducted.展开更多
An S-band frequency synthesizer for a stepped-frequency radar is presented. This frequen- cy synthesizer is based on a direct digital synthesizer ( DDS ) -driven wideband phase-locked loop (PLL) architecture which...An S-band frequency synthesizer for a stepped-frequency radar is presented. This frequen- cy synthesizer is based on a direct digital synthesizer ( DDS ) -driven wideband phase-locked loop (PLL) architecture which can achieve low spurious noise and rapid frequency hopping simultaneous- ly. The mechanism of introducing high level spurs by the images of DDS digital to analog convertor (DAC) output is analyzed. A novel DDS frequency planning method is proposed to ensure low col- ored noise within the entire bandwidth. The designed output frequency range is 3. 765 -4. 085 GHz, and the step size is 5 MHz with frequency agility of less than 1 μs. Measured results demonstrate that the average spurious free dynamic range (SFDR) is about 64 dBc in a 320 MHz bandwidth.展开更多
In order to solve problems in high dynamic environment, a frequency-locked loop (FLL) assisted phase-locked loop (PLL) is put forward for carrier tracking. On the basis of the analysis of discriminators, the total...In order to solve problems in high dynamic environment, a frequency-locked loop (FLL) assisted phase-locked loop (PLL) is put forward for carrier tracking. On the basis of the analysis of discriminators, the total phase error of the tracking loop is analyzed and a general error expression is derived. By using linearization and Jaffe-Rechtin coefficients, the performance of a special first order FLL-assisted second order PLL is analyzed to get a closed expression. Analysis results and simula- tions show that there exist an optimal FLL loop bandwidth and a optimal PLL loop bandwidth which can make the phase jitter much less than that when the PLL is used alone.展开更多
This paper proposes a novel Gm-C loop filter instead of a conventional passive loop filter used in a phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence ...This paper proposes a novel Gm-C loop filter instead of a conventional passive loop filter used in a phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced. Furthermore, the MASH 1-1-1 sigma-delta (ZA) modulator is adopted for performing the fractional division number and hence improves the phase noise as well. Measured results show that the locked phase noise is -114.1 dBc/Hz with lower Gm-C bandwidth and -111.7 dBm/C with higher Gm-C bandwidth at 1 MHz offset from carrier of 5.68 GHz. Including pads and built-in Gm-C filter, the chip area of the proposed frequency synthesizer is 1.06 mm2. The output power is -8.69 dBm at 5.68 CHz and consumes 56 mW with an off-chip buffer from 1.8-V supply voltage.展开更多
The design of a 2. 488 Gbit/s clock and data recovery (CDR) If for synchronous digital hierarchy (SDH) STM-16 receiver is described. Based on the injected phase-locked loop (IPLL) and D-flip flop architectures, ...The design of a 2. 488 Gbit/s clock and data recovery (CDR) If for synchronous digital hierarchy (SDH) STM-16 receiver is described. Based on the injected phase-locked loop (IPLL) and D-flip flop architectures, the CDR IC was implemented in a standard 0. 35 μan complementary metal-oxide-semiconductor (CMOS) technology. With 2^31 -1 pseudorandom bit sequences (PRBS) input, the sensitivity of data recovery circuit is less than 20 mV with 10^-12 bit error rate (BER). The recovered clock shows a root mean square (rms) jitter of 2. 8 ps and a phase noise of - 110 dBc/Hz at 100 kHz offset. The capture range of the circuit is larger than 40 MHz. With a 5 V supply, the circuit consumes 680 mW and the chip area is 1.49 mm × 1 mm.展开更多
基金supported by the Pioneer Hundred Talents Program,Chinese Academy of Sciences.
文摘CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.
基金The National Natural Science Foundation of China(No. 60974116 )the Research Fund of Aeronautics Science (No.20090869007)Specialized Research Fund for the Doctoral Program of Higher Education (No. 200902861063)
文摘In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system (MEMS) gyroscope are analyzed in principle. A novel drive circuit for the MEMS gyroscope in digital closed-loop control is proposed, which utilizes a digital phase-locked loop (PLL) in frequency control and an automatic gain control (AGC) method in amplitude control. A digital processing circuit with a field programmable gate array (FPGA) is designed and the experiments are carried out. The results indicate that when the temperature changes, the drive frequency can automatically track the resonant frequency of gyroscope in drive mode and that of the oscillating amplitude holds at a set value. And at room temperature, the relative deviation of the drive frequency is 0.624 ×10^-6 and the oscillating amplitude is 8.0 ×10^-6, which are 0. 094% and 18. 39% of the analog control program, respectively. Therefore, the control solution of the digital PLL in frequency and the AGC in amplitude is feasible.
基金supported by the National Natural Science Foundation of China(Grant No.61307128)the National Basic Research Program of China(GrantNo.2010CB327505)+1 种基金the Specialized Research Found for the Doctoral Program of Higher Education of China(Grant No.20131101120027)the Basic Research Foundation of Beijing Institute of Technology of China(Grant No.20120542015)
文摘We propose a novel hybrid phase-locked loop (PLL) architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator (VCO) and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor (CMOS) process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.
基金supported by the National Natural Science Foundation of China under Grant 62004028,62090041the Science Foundation of Sichuan under Grant 2022NSFSC0927.
文摘This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power,jitter and area.An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analyt-ically and benchmarked with respect to their figure-of-merit(FoM).The paper also summarizes the key concerns on the selection of dif-ferent circuit techniques to optimize the clock performance under dif-ferent scenarios.
文摘Chirp超宽带具有峰值平均功率比(peak to average power ratio,PAPR)接近为1、测距定位能力强等优势,能够有效解决传统的超宽带技术存在的PAPR过大、传输距离短等问题,设计并产生Chirp超宽带信号是实现该通信系统的关键技术之一。提出了一种高性能Chirp超宽带信号源方案,通过采用现场可编程门阵列(field-programma-ble gate array,FPGA)控制直接数字频率合成(direct digital synthesis,DDS)芯片AD9956产生低频Chirp信号,并结合锁相环(phase locked loop,PLL)技术实现带宽扩展,从而获得Chirp超宽带信号。实验表明,所设计的Chirp超宽带信号源具有结构简单、可编程、可扩展、性能好及实用性强等优点。
文摘A digital phase-locked loop (DPLL) based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works from 60 to 600MHz at a supply voltage of 1.8V. It also features a fraetional-N synthesizer with digital 2nd-order sigma-delta noise shaping, which can achieve a short lock time,a high frequency resolution,and an improved phase-noise spectrum. The DPLL has been implemented in SMIC 0. 18μm 1.8V 1P6M CMOS technology. The peak-to-peak jitter is less than 0. 8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider.
基金supported by the National Natural Science Foundation of China(No.51677142)the National Key R&D Program of China(No.2016YFB0900600)。
文摘Voltage source converter based high-voltage direct current(VSC-HVDC)transmission technology has been extensively employed in power systems with a high penetration of renewable energy resources.However,connecting a voltage source converter(VSC)to an AC weak grid may cause the converter system to become unstable.In this paper,a phase-shift phaselocked loop(PS-PLL)is proposed wherein a back electromotive force(BEMF)observer is added to the conventional phaselocked loop(PLL).The BEMF observer is used to observe the voltage of the infinite grid in the stationaryαβframe,which avoids the problem of inaccurate observations of the grid voltage in the dq frame that are caused by the output phase angle errors of the PLL.The VSC using the PS-PLL can operate as if it is facing a strong grid,thus enhancing the stability of the VSC-HVDC system.The proposed PS-PLL only needs to be properly modified on the basis of a traditional PLL,which makes it easy to implement.In addition,because it is difficult to obtain the exact impedance of the grid,the influence of shortcircuit ratio(SCR)estimation errors on the performance of the PS-PLL is also studied.The effectiveness of the proposed PSPLL is verified by the small-signal stability analysis and timedomain simulation.
基金This work is supported in part by the National Natural Science Foundation of China(No.51807089,51877104)in part by the Natural Science Foundation of Jiangsu Province(No.BK20180432).
文摘In renewable power generation systems,ensuring the synchronization of the inverter and the power grid is crucial for the stable operation of grid-connected inverters.Nowadays,the phase-locked loop(PLL)technology has become a widely used grid synchronization method because of its simple implementation and robustness under various grid conditions.Even though a lot of PLLs have been proposed,an overview and comparative analysis of multiple PLLs can be helpful for practical applications.In addition,the weak grid condition is a great challenge for the system.Therefore,this study first presents an overview of the existing PLLs together with their general structures and basic working principles.Depending on the implementation of the phase detector,the PLL can be divided into three categories:power-based PLL(pPLL),orthogonal-signalgenerator-based PLL(OSG-PLL)and adaptive-filter-based PLL(AF-PLL).Then,from the above classification,seven typical single-phase PLLs are selected for further study.Finally,some test results are given,and a comprehensive evaluation of the selected PLLs under different grid conditions is conducted.
基金Supported by the Fund of National Defense Industry Innova-tive Team(231)
文摘An S-band frequency synthesizer for a stepped-frequency radar is presented. This frequen- cy synthesizer is based on a direct digital synthesizer ( DDS ) -driven wideband phase-locked loop (PLL) architecture which can achieve low spurious noise and rapid frequency hopping simultaneous- ly. The mechanism of introducing high level spurs by the images of DDS digital to analog convertor (DAC) output is analyzed. A novel DDS frequency planning method is proposed to ensure low col- ored noise within the entire bandwidth. The designed output frequency range is 3. 765 -4. 085 GHz, and the step size is 5 MHz with frequency agility of less than 1 μs. Measured results demonstrate that the average spurious free dynamic range (SFDR) is about 64 dBc in a 320 MHz bandwidth.
文摘In order to solve problems in high dynamic environment, a frequency-locked loop (FLL) assisted phase-locked loop (PLL) is put forward for carrier tracking. On the basis of the analysis of discriminators, the total phase error of the tracking loop is analyzed and a general error expression is derived. By using linearization and Jaffe-Rechtin coefficients, the performance of a special first order FLL-assisted second order PLL is analyzed to get a closed expression. Analysis results and simula- tions show that there exist an optimal FLL loop bandwidth and a optimal PLL loop bandwidth which can make the phase jitter much less than that when the PLL is used alone.
文摘This paper proposes a novel Gm-C loop filter instead of a conventional passive loop filter used in a phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced. Furthermore, the MASH 1-1-1 sigma-delta (ZA) modulator is adopted for performing the fractional division number and hence improves the phase noise as well. Measured results show that the locked phase noise is -114.1 dBc/Hz with lower Gm-C bandwidth and -111.7 dBm/C with higher Gm-C bandwidth at 1 MHz offset from carrier of 5.68 GHz. Including pads and built-in Gm-C filter, the chip area of the proposed frequency synthesizer is 1.06 mm2. The output power is -8.69 dBm at 5.68 CHz and consumes 56 mW with an off-chip buffer from 1.8-V supply voltage.
文摘The design of a 2. 488 Gbit/s clock and data recovery (CDR) If for synchronous digital hierarchy (SDH) STM-16 receiver is described. Based on the injected phase-locked loop (IPLL) and D-flip flop architectures, the CDR IC was implemented in a standard 0. 35 μan complementary metal-oxide-semiconductor (CMOS) technology. With 2^31 -1 pseudorandom bit sequences (PRBS) input, the sensitivity of data recovery circuit is less than 20 mV with 10^-12 bit error rate (BER). The recovered clock shows a root mean square (rms) jitter of 2. 8 ps and a phase noise of - 110 dBc/Hz at 100 kHz offset. The capture range of the circuit is larger than 40 MHz. With a 5 V supply, the circuit consumes 680 mW and the chip area is 1.49 mm × 1 mm.