Adaptive Digital Predistortion Schemes to Linearize RF Power Amplifiers with Memory Effects

To compensate for nonlinear distortion introduced by RF power amplifiers （PAs） with memory effects, two correlated models, namely an extended memory polynomial （EMP） model and a memory lookup table （LUT） model, are proposed for predistorter design. Two adaptive digital predistortion （ADPD） schemes with indirect learning architecture are presented. One adopts the EMP model and the recursive least square （RLS） algorithm, and the other utilizes the memory LUT model and the least mean square （LMS） algorithm. Simulation results demonstrate that the EMP-based ADPD yields the best linearization performance in terms of suppressing spectral regrowth. It is also shown that the ADPD based on memory LUT makes optimum tradeoff between performance and computational complexity.

Robust Digital Predistortion for LTE/5G Power Amplifiers Utilizing Negative Feedback Iteration

A robust digital predistortion(DPD)technique utilizing negative feedback iteration is introduced for linearizing power amplifiers(PAs)in long term evolution(LTE)/5G systems.Different from the conventional direct learning and indirect learning structure,the proposed DPD suggests a two-step method to identify the predistortion.Firstly,a negative feedback based iteration is used to estimate the optimal DPD signal.Then the corresponding DPD parameters are extracted by forward modeling with the input signal and optimal DPD signal.The iteration can be applied to both single-band and dual-band PAs,which will achieve superior linear performance than the conventional direct learning DPD while having a relatively low computational complexity.The measurement is carried out on a broadband Doherty PA(DPA)with a 200 MHz bandwidth LTE signal at 2.1 GHz,and on a 5G DPA with two 10 MHz LTE signals at 3.4/3.6 GHz for validation in dual-band scenarios.

Digital Predistortion and Measurement Method

Digital PreDistortion(DPD)is a very useful method to improve the linearity of Power Amplifiers(PAs)for LTE and upcoming 5 G networks.As the spectrum resources are becoming more and more crowded,and the communications bandwidth are broader,the ACPR(Adjacent Channel Leakage Ratio)is very important to communication systems.DPD is one of the useful means for PA to reduce ACPR.This article demonstrates what DPD is and how DPD is achieved,the measurement of the Digital Distortion of a PA using a vector generator and vector analyzer,and the measurement results has been discussed.

A Strong Anti-Jamming Algorithm Based on FPGA for Estimating Loop Delay in Digital Predistortion System

At present what are the key points focused in the research of loop-delay estimation for the digital predistorter in the radio frequency （RF） power amplifier system is reducing its complexity of engineering realization and improving anti-jamming ability and computational speed. Besides, opening up its application scope should be contained. For these targets, a novel method including integer loop delay estimation and fractional part is proposed. The integer part applies amplitude-difference summation function and the fractional one adopts the method of finite impulse response （FIR） linear interpolation. The algorithm finds wide applications. What is more, strong anti-jamming ability and low complexity are also its merits. Simulation results support the above opinion. Digital predistortion （DPD） system based on this algorithm achieves good performance.

Low sampling rate technique based frequency-domain random demodulation for broadband digital predistortion

This paper proposes a combination technique of the frequency-domain random demodulation（FRD） and the broadband digital predistorter（DPD）. This technique can linearize the power amplifiers（PAs） at a low sampling rate in the feedback loop. Based on the theory of compressed sensing（CS）, the FRD method preprocesses the original signal using the frequency domain sampling signal with different stages through multiple parallel channels. Then the FRD method is applied to the broadband DPD system to restrict the sampling process in the feedback loop. The proposed technique is assessed using a 30 W Class-F wideband PA driven by a 20 MHz orthogonal frequency division multiplexing（OFDM） signal, and a 40 W Ga N Doherty PA driven by a 40 MHz 4-carrier long-term evolution（LTE） signal. The simulation and experimental results show that good linearization performance can be achieved at a lower sampling rate with about- 24 d Bc adjacent channel power ratio（ACPR） improvement by applying the proposed combination technique FRD-DPD. Furthermore, the performance of normalized mean square error（NMSE） and error vector magnitude（EVM） also has been much improved compared with the conventional technique.

FPGA Implementation of a Power Amplifier Linearizer for an ETSI-SDR OFDM Transmitter

Most satellite digital radio （SDR） systems use orthogonal frequency-division multiplexing （OFDM） transmission, which means that variable envelope signals are distorted by the RF power amplifier （PA）. It is customary to back off the input power to the PA to avoid the PA nonlinear region of operation. In this way, linearity can be achieved at the cost of power efficiency. Another attractive option is to use a linearizer, which compensates for the nonlinear effects of the PA. In this paper, an OFDM transmitter conforming to European Telecommunications Standard Institute SDR Technical Specifications 2007-2008 was designed and implemented on a low-cost field-programmable gate array （FPGA） platform. A weakly nonlinear PA, operating in the L-band SDR frequency, was used for signal transmission. An adaptive linearizer was designed and implemented on the same FPGA device using digital predistortion to correct the undesired effects of the PA on the transmitted signal. Test results show that spectral distortion can be suppressed between 6-9 dB using the designed linearizer when the PA is driven close to its saturation region.

Low-cost FPGA implementation of 2D digital pre-distorter for concurrent dual-band power amplifier

This paper proposes a low-cost hardware architecture based on concurrent dual-band digital pre-distorter （DPD）. The architecture is implemented on field programmable gate array （FPGA） to compensate for the nonlinearity of the concurrent dual-band power amplifier （PA）. This implementation introduces a novel model complexity reduction technique into system, namely, time-division multiplexing for out-of-band lookup tables （LUTs） sharing. Performances are evaluated with an experimental test setup using a wideband class-F PA. The dual-band signal center frequency separated by 80 MHz. Lower and upper center frequency are located at 2.61 GHz and 2.69 GHz, respectively. This novel DPD implementation maintains excellent performance, but uses hardware resources reduced by 29.17% compared with conventional approaches. The results show that the adjacent channel power ratio （ACPR） is less than -59 dBc and normalized mean square error （NMSE） is around - 62dB for lower sideband （LSB） and - 63dB for upper sideband （USB）.

Performance of a recursive algorithm for polynomial predistorter design

In this article, based on least square estimation, a recursive algorithm for indirect learning structure predistorter is introduced. Simulation results show that of all polynomial predistorter nonlinear terms, higher-order （higher than 7th-order） nonlinear terms are so minor that they can be omitted in practical predistorter design. So, it is unnecessary to construct predistorter with higher-order polynomials, and the algorithm will always be stable. Further results show that even when 15th-order polynomial model is used, the algorithm is convergent after 10 iterations, and it can improve out-band spectrum of 20 MHz bandwidth signal by 64 dB, with a 1.2×10^11 matrix condition number.