A near-infrared single-photon detection system is established by using pigtailed InGaAs/InP avalanche photodiodes. With a 50GHz digital sampling oscilloscope, the function and process of gated-mode （Geiger-mode） sin...A near-infrared single-photon detection system is established by using pigtailed InGaAs/InP avalanche photodiodes. With a 50GHz digital sampling oscilloscope, the function and process of gated-mode （Geiger-mode） single-photon detection are intuitionally demonstrated for the first time. The performance of the detector as a gated-mode single-photon counter at wavelengths of 1310 and 1550nm is investigated. At the operation temperature of 203K,a quantum efficiency of 52% with a dark count probability per gate of 2.4 × 10 ^-3 ,and a gate pulse repetition rate of 50kHz are obtained at 1550nm. The corresponding parameters are 43%, 8.5 × 10^-3 , and 200kHz at 238K.展开更多
A single CMOS image sensor based on a 0.35μm process along with its design and implementation is introduced. The architecture of an active pixel sensor is used in the chip. The fill factor of a pixel cell can reach 4...A single CMOS image sensor based on a 0.35μm process along with its design and implementation is introduced. The architecture of an active pixel sensor is used in the chip. The fill factor of a pixel cell can reach 43%,higher than the traditional factor of 30%. Moreover, compared with the conventional method whose fixed pattern noise （FPN） is around 0.5%, a dynamic digital double sampling technique is developed, which possesses simpler circuit architecture and a better FPN suppression outcome. The CMOS image sensor chip is implemented in the 0.35μm mixed signal process of a Chartered by MPW. The experimental results show that the chip operates welt,with an FPN of about 0.17%.展开更多
To reduce the charge-coupled device(CCD)readout noise and improve the detection ability under low illumination and dim targets,a new low-noise CCD signal processing technology-CCD digital denoiseis gradually being emp...To reduce the charge-coupled device(CCD)readout noise and improve the detection ability under low illumination and dim targets,a new low-noise CCD signal processing technology-CCD digital denoiseis gradually being employed in aerospace detection and other fields.In this study,the main readout noise of CCD detectors and its characteristics are analyzed.A CCD digital denoise system and an experimental platform are designed as well as established by using a PCIe data acquisition card.According to the characteristics of readout noise,some digital filters are analyzed and designed based on distributed kernel coefficient,and the optimal kernel coefficients are obtained through iteration.Then,CCD signal and filter model are established,and the optimal filter is designed to apply to the digital denoise system.Finally,according to the image data obtained from the system,the performance of the digital denoise system and digital filtering algorithm is evaluated and compared.At 500 kHz and 1 MHz CCD readout rates,the denoising performance of the optimal filter designed in the experiment is 16%-32%higher than that of the digital filter with kernel distribution coefficient,and 50%-60%higher than that of the traditional correlated double sampling technology.展开更多
A single Complementary Metal Oxide Semiconductor (CMOS) image sensor based on 0.35μm process along with its design and implementation is introduced in this paper. The pixel ar-chitecture of Active Pixel Sensor (APS) ...A single Complementary Metal Oxide Semiconductor (CMOS) image sensor based on 0.35μm process along with its design and implementation is introduced in this paper. The pixel ar-chitecture of Active Pixel Sensor (APS) is used in the chip,which comprises a 256×256 pixel array together with column amplifiers,scan array circuits,series interface,control logic and Analog-Digital Converter (ADC). With the use of smart layout design,fill factor of pixel cell is 43%. Moreover,a new method of Dynamic Digital Double Sample (DDDS) which removes Fixed Pattern Noise (FPN) is used. The CMOS image sensor chip is implemented based on the 0.35μm process of chartered by Multi-Project Wafer (MPW). This chip performs well as expected.展开更多
Intelligent substations adopt various kinds of new technologies, including information sharing technology based on IEC61850, digital sampling technology, synchronization technology, and network transmission technology...Intelligent substations adopt various kinds of new technologies, including information sharing technology based on IEC61850, digital sampling technology, synchronization technology, and network transmission technology. Relay protection equipment faces all the challenges brought by the application of these new technologies. After analyzing the demand for test, the authors propose testing methods and technical requirements targeting the test items in great need, including ICD model file test, digital interface performance test, coordination performance test with merging unit and smart terminal, network pressure test. And the problems occurring during the tests are summarized.展开更多
文摘A near-infrared single-photon detection system is established by using pigtailed InGaAs/InP avalanche photodiodes. With a 50GHz digital sampling oscilloscope, the function and process of gated-mode （Geiger-mode） single-photon detection are intuitionally demonstrated for the first time. The performance of the detector as a gated-mode single-photon counter at wavelengths of 1310 and 1550nm is investigated. At the operation temperature of 203K,a quantum efficiency of 52% with a dark count probability per gate of 2.4 × 10 ^-3 ,and a gate pulse repetition rate of 50kHz are obtained at 1550nm. The corresponding parameters are 43%, 8.5 × 10^-3 , and 200kHz at 238K.
文摘A single CMOS image sensor based on a 0.35μm process along with its design and implementation is introduced. The architecture of an active pixel sensor is used in the chip. The fill factor of a pixel cell can reach 43%,higher than the traditional factor of 30%. Moreover, compared with the conventional method whose fixed pattern noise （FPN） is around 0.5%, a dynamic digital double sampling technique is developed, which possesses simpler circuit architecture and a better FPN suppression outcome. The CMOS image sensor chip is implemented in the 0.35μm mixed signal process of a Chartered by MPW. The experimental results show that the chip operates welt,with an FPN of about 0.17%.
基金the National Program on Key Basic Research Project(973 Program)(No.6132570201).
文摘To reduce the charge-coupled device(CCD)readout noise and improve the detection ability under low illumination and dim targets,a new low-noise CCD signal processing technology-CCD digital denoiseis gradually being employed in aerospace detection and other fields.In this study,the main readout noise of CCD detectors and its characteristics are analyzed.A CCD digital denoise system and an experimental platform are designed as well as established by using a PCIe data acquisition card.According to the characteristics of readout noise,some digital filters are analyzed and designed based on distributed kernel coefficient,and the optimal kernel coefficients are obtained through iteration.Then,CCD signal and filter model are established,and the optimal filter is designed to apply to the digital denoise system.Finally,according to the image data obtained from the system,the performance of the digital denoise system and digital filtering algorithm is evaluated and compared.At 500 kHz and 1 MHz CCD readout rates,the denoising performance of the optimal filter designed in the experiment is 16%-32%higher than that of the digital filter with kernel distribution coefficient,and 50%-60%higher than that of the traditional correlated double sampling technology.
文摘A single Complementary Metal Oxide Semiconductor (CMOS) image sensor based on 0.35μm process along with its design and implementation is introduced in this paper. The pixel ar-chitecture of Active Pixel Sensor (APS) is used in the chip,which comprises a 256×256 pixel array together with column amplifiers,scan array circuits,series interface,control logic and Analog-Digital Converter (ADC). With the use of smart layout design,fill factor of pixel cell is 43%. Moreover,a new method of Dynamic Digital Double Sample (DDDS) which removes Fixed Pattern Noise (FPN) is used. The CMOS image sensor chip is implemented based on the 0.35μm process of chartered by Multi-Project Wafer (MPW). This chip performs well as expected.
文摘Intelligent substations adopt various kinds of new technologies, including information sharing technology based on IEC61850, digital sampling technology, synchronization technology, and network transmission technology. Relay protection equipment faces all the challenges brought by the application of these new technologies. After analyzing the demand for test, the authors propose testing methods and technical requirements targeting the test items in great need, including ICD model file test, digital interface performance test, coordination performance test with merging unit and smart terminal, network pressure test. And the problems occurring during the tests are summarized.
