为满足数字存储示波器(DSO)大流量实时数据显示的需要,本文设计了一种以A ltera FPGA和T I C 5000DSP为核心的高性能液晶屏(LCD)显示控制系统。该系统只需主机直接提供采样数据和少量控制字,便可自动生成显示所需的各种菜单,完成对采样...为满足数字存储示波器(DSO)大流量实时数据显示的需要,本文设计了一种以A ltera FPGA和T I C 5000DSP为核心的高性能液晶屏(LCD)显示控制系统。该系统只需主机直接提供采样数据和少量控制字,便可自动生成显示所需的各种菜单,完成对采样数据的处理,产生输出波形,并驱动LCD以恒定刷屏速率进行显示。系统减轻了主机负担,实现了LCD高速数据更新,提供了灵活的接口电路,并在测试中获得了每秒80帧的波形更新速率。展开更多
基于传统单处理器系统有限的数据处理能力正逐渐成为示波器整机的瓶颈,作者设计了一种基于可编程系统芯片(System on programm ablech ip,SOPC)结构,用于1 GHz采样速率数字存储示波器(Digital storageos-cilloscope,DSO)的数据处理系统...基于传统单处理器系统有限的数据处理能力正逐渐成为示波器整机的瓶颈,作者设计了一种基于可编程系统芯片(System on programm ablech ip,SOPC)结构,用于1 GHz采样速率数字存储示波器(Digital storageos-cilloscope,DSO)的数据处理系统。系统中,根据模数转换器特征为其设计了具有数据缓存功能的接口单元;以A ltera Nios II/f软核为基础完成了专用微处理器的设计;针对DSO数据处理特征构建了4个并行处理电路;同时,系统还实现了液晶显示屏(LCD)的硬件驱动。SOPC结构的引入,使得该系统在具备强大数据处理能力的同时,具有低功耗和高集成度的特点。展开更多
This paper describes the development of a timer based voltage to frequency converter(V FC).Timer LM555is used in astable multivibrator mode with two OPTO-LDRs(light dependent resistors)in the circuitry.The frequency o...This paper describes the development of a timer based voltage to frequency converter(V FC).Timer LM555is used in astable multivibrator mode with two OPTO-LDRs(light dependent resistors)in the circuitry.The frequency of timer output waveform which is measured using a digital storage oscillator(DSO)is almost linearly proportional to the applied input voltage.Hence we obtain a linear relationship between the frequency of timer output waveform and the input voltage.Because of its quasi-digital output,the main advantages of this developed converter are linear input-output relationship,small size,easy portabilityand high cost performance.In addition,the timer output waveform can be directly interfaced with personal computer or microprocessor/microcontroller for further processing of the input voltage signal without intervening any analog-to-digital converter(ADC).展开更多
文摘为满足数字存储示波器(DSO)大流量实时数据显示的需要,本文设计了一种以A ltera FPGA和T I C 5000DSP为核心的高性能液晶屏(LCD)显示控制系统。该系统只需主机直接提供采样数据和少量控制字,便可自动生成显示所需的各种菜单,完成对采样数据的处理,产生输出波形,并驱动LCD以恒定刷屏速率进行显示。系统减轻了主机负担,实现了LCD高速数据更新,提供了灵活的接口电路,并在测试中获得了每秒80帧的波形更新速率。
文摘基于传统单处理器系统有限的数据处理能力正逐渐成为示波器整机的瓶颈,作者设计了一种基于可编程系统芯片(System on programm ablech ip,SOPC)结构,用于1 GHz采样速率数字存储示波器(Digital storageos-cilloscope,DSO)的数据处理系统。系统中,根据模数转换器特征为其设计了具有数据缓存功能的接口单元;以A ltera Nios II/f软核为基础完成了专用微处理器的设计;针对DSO数据处理特征构建了4个并行处理电路;同时,系统还实现了液晶显示屏(LCD)的硬件驱动。SOPC结构的引入,使得该系统在具备强大数据处理能力的同时,具有低功耗和高集成度的特点。
文摘This paper describes the development of a timer based voltage to frequency converter(V FC).Timer LM555is used in astable multivibrator mode with two OPTO-LDRs(light dependent resistors)in the circuitry.The frequency of timer output waveform which is measured using a digital storage oscillator(DSO)is almost linearly proportional to the applied input voltage.Hence we obtain a linear relationship between the frequency of timer output waveform and the input voltage.Because of its quasi-digital output,the main advantages of this developed converter are linear input-output relationship,small size,easy portabilityand high cost performance.In addition,the timer output waveform can be directly interfaced with personal computer or microprocessor/microcontroller for further processing of the input voltage signal without intervening any analog-to-digital converter(ADC).