A dual-mode analog baseband with digital-assisted DC-offset calibration （DCOC） for WCDMA/GSM receiver is presented. A digital-assisted DCOC is proposed to solve the DC-offset problem by removing the DC- offset compo...A dual-mode analog baseband with digital-assisted DC-offset calibration （DCOC） for WCDMA/GSM receiver is presented. A digital-assisted DCOC is proposed to solve the DC-offset problem by removing the DC- offset component only. This method has no bandwidth sacrifice. After calibration the measured output residual offset voltage is within 5 mV at most gain settings and the IIP2 is more than 60 dBm. The baseband is designed to be reconfigurable at bandwidths of 200 kHz and 2.1 MHz. Total baseband gain can be programmed from 6 to 54 dB. The chip is manufactured with 0.13μm CMOS technology and consumes 10 mA from a 1.5 V supply in the GSM mode including an on-chip buffer while the core area occupies 1.2 mm^2.展开更多
This paper presents a continuously and widely tunable analog baseband chain with a digital-assisted calibration scheme implemented on a 0.13μm CMOS technology.The analog baseband is compliant with several digital bro...This paper presents a continuously and widely tunable analog baseband chain with a digital-assisted calibration scheme implemented on a 0.13μm CMOS technology.The analog baseband is compliant with several digital broadcasting system（DBS） standards,including DVB-S,DVB-S2,and ABS-S.The cut-off frequency of the baseband circuit can be changed continuously from 4.5 to 32 MHz.The gain adjustment range is from 6 to 55.5 dB with 0.5 dB step.The calibration includes automatic frequency tuning（AFT） and automatic DC offset calibration （DCOC） to achieve less than 6%cut-off frequency deviation and 3 mV residual output offset.The out-of-band IIP2 and IIP3 of the overall chain are 45 dBm and 18 dBm respectively,while the input referred noise（IRN） is 17.4 nV/√Hz.All circuit blocks are operated at 2.8 V from LDO and consume current of 20.4 mA in the receiving mode.展开更多
This paper presented an automatic gain control （AGC） circuit suitable for FM/cw ladar. The proposed architecture was based on two-stage variable gain amplifier （VGA） chain with a novel DC offset canceller circuit,...This paper presented an automatic gain control （AGC） circuit suitable for FM/cw ladar. The proposed architecture was based on two-stage variable gain amplifier （VGA） chain with a novel DC offset canceller circuit, which contained an improved Gilbert cell and a Gm-C feedback loop. To keep the VGA with a linearity in dB characteristic, an improved exponential gain control circuit was introduced. The AGC was implemented in 0.18 gm standard CMOS process. Simulation and measurement results verified that its gain ranged from -20 dB to 30 dB, and band- width ranged from 100 kHz to 10 MHz. Its power consumption was 19.8 mW under a voltage supply of 3.3 V.展开更多
This paper designs a binary-weighted programmable gain amplifier（PGA） with a DC offset cancellation （DCOC） circuit and an AB-class output buffer.The PGA adopts the circuit topology of a differential amplifier with...This paper designs a binary-weighted programmable gain amplifier（PGA） with a DC offset cancellation （DCOC） circuit and an AB-class output buffer.The PGA adopts the circuit topology of a differential amplifier with diode-connected loads.Simulation shows that the performance of the PGA is not sensitive to temperature and process variation.According to test results,controlled by a digital signal of six bits,the PGA can realize a dynamic gain of-2 to 61 dB,and a gain step of 1 dB with a step error within±0.38 dB.The minimum 3 dB bandwidth is 92 MHz.At low-gain mode,IIP3 is 17 dBm,and a 1 dB compression point can reach 5.7 dBm.The DCOC circuit enables the amplifier to be used in a direct-conversion receiver and the AB-class output buffer circuit reduces the overall static power consumption.展开更多
A high speed inductorless limiting amplifier （LA） in an optical communication receiver with the work- ing speed up to 20 Gb/s is presented. The LA includes an input matching network, a four-stage 3rd order amplifier...A high speed inductorless limiting amplifier （LA） in an optical communication receiver with the work- ing speed up to 20 Gb/s is presented. The LA includes an input matching network, a four-stage 3rd order amplifier core, an output buffer for the test and a DC offset cancellation （DCOC）. It uses the active interleaving feedback technique both to broaden the bandwidth and achieve the flatness response. Based on our careful analysis of the DCOC and stability, an error amplifier is added to the DCOC loop in order to keep the offset voltage reasonable. Fabricated in the 65 nm CMOS technology, the LA only occupies an area of 0.45 × 0.25 mm2 （without PAD）. The measurement results show that the LA achieves a differential voltage gain of 37 dB, and a 3-dB bandwidth of 16.5 GHz. Up to 26.5 GHz, the Sddlm and Sdd22 are less than -16 dB and -9 dB. The chip excluding buffer is supplied by 1.2 V VDD and draws a current of 50 mA.展开更多
A design of high dynamic range linear radio frequency power detector （PD）, aimed for transmitter carrier leakage suppression is presented in this paper. Based on the logarithmic amplifier principle, this detector ut...A design of high dynamic range linear radio frequency power detector （PD）, aimed for transmitter carrier leakage suppression is presented in this paper. Based on the logarithmic amplifier principle, this detector utilizes the successive detection method to achieve a high dynamic range in the radio frequency band. In order to increase sensitivity, a low noise amplifier （LNA） is placed in the front of this detector. DC coupling is adopted in this architecture to reduce parasitics and save area, but this will unavoidably cause DC offsets in the circuit which are detrimental to the dynamic range. So a DC offset cancelling （DCOC） technique is proposed to solve the problem. Finally, this detector was fabricated in the SMIC 0.13μm CMOS process. The measured results show that it achieves a wide dynamic range of 50 dB/40 dB with log errors in 4-1 dB at 900 MHz/2 GHz, while draws 16 mA from a 1.5 V power supply. The active chip area is 0.27×0.67 mm2.展开更多
An analog baseband circuit of high linearity and high gain accuracy for a digital audio broadcasting receiver is implemented in a 0.18-μm RFCMOS process.The circuit comprises a 3rd-order active-RC complex filter（CF...An analog baseband circuit of high linearity and high gain accuracy for a digital audio broadcasting receiver is implemented in a 0.18-μm RFCMOS process.The circuit comprises a 3rd-order active-RC complex filter（CF） and a programmable gain amplifier（PGA）.An automatic tuning circuit is also designed to tune the CF＇s pass band.Instead of the class-A fully differential operational amplifier（FDOPA） adopted in the conventional CF and PGA design,a class-AB FDOPA is specially employed in this circuit to achieve a higher linearity and gain accuracy for its large current swing capability with lower static current consumption.In the PGA circuit,a novel DC offset cancellation technique based on the MOS resistor is introduced to reduce the settling time significantly.A reformative switching network is proposed,which can eliminate the switch resistor＇s influence on the gain accuracy of the PGA.The measurement result shows the gain range of the circuit is 10-50 dB with a 1-dB step size,and the gain accuracy is less than ±0.3 dB.The OIP3 is 23.3 dBm at the gain of 10 dB.Simulation results show that the settling time is reduced from 100 to 1 ms.The image band rejection is about 40 dB.It only draws 4.5 mA current from a 1.8 V supply voltage.展开更多
An analog baseband circuit for a direct conversion wireless local area network（WLAN） transceiver in a standard 0.13-μm CMOS occupying 1.26 mm^2 is presented.The circuit consists of active-RC receiver（RX） 4th orde...An analog baseband circuit for a direct conversion wireless local area network（WLAN） transceiver in a standard 0.13-μm CMOS occupying 1.26 mm^2 is presented.The circuit consists of active-RC receiver（RX） 4th order elliptic lowpass filters（LPFs）,transmitter（TX） 3rd order Chebyshev LPFs,RX programmable gain amplifiers （PGAs） with DC offset cancellation（DCOC） servo loops,and on-chip output buffers.The RX baseband gain can be programmed in the range of -11 to 49 dB in 2 dB steps with 50-30.2 nV/（Hz）^（1/2） input referred noise（IRN） and a 21 to -41 dBm in-band 3rd order interception point（IIP3）.The RX/TX LPF cutoff frequencies can be switched between 5 MHz,10 MHz,and 20 MHz to fulfill the multimode 802.11b/g/n requirements.The TX baseband gain of the I/Q paths are tuned separately from -1.6 to 0.9 dB in 0.1 dB steps to calibrate TX 1/Q gain mismatches.By using an identical integrator based elliptic filter synthesis method together with global compensation applied to the LPF capacitor array,the power consumption of the RX LPF is considerably reduced and the proposed chip draws 26.8 mA/8 mA by the RX/TX baseband paths from a 1.2 V supply.展开更多
基金Project supported by the National High Technology Research and Development Program of China(Nos.2009AA01Z261,2009ZX01031- 003 -002 )
文摘A dual-mode analog baseband with digital-assisted DC-offset calibration （DCOC） for WCDMA/GSM receiver is presented. A digital-assisted DCOC is proposed to solve the DC-offset problem by removing the DC- offset component only. This method has no bandwidth sacrifice. After calibration the measured output residual offset voltage is within 5 mV at most gain settings and the IIP2 is more than 60 dBm. The baseband is designed to be reconfigurable at bandwidths of 200 kHz and 2.1 MHz. Total baseband gain can be programmed from 6 to 54 dB. The chip is manufactured with 0.13μm CMOS technology and consumes 10 mA from a 1.5 V supply in the GSM mode including an on-chip buffer while the core area occupies 1.2 mm^2.
基金supported by the National Natural Science Foundation of China(Nos.61176093,51072171)
文摘This paper presents a continuously and widely tunable analog baseband chain with a digital-assisted calibration scheme implemented on a 0.13μm CMOS technology.The analog baseband is compliant with several digital broadcasting system（DBS） standards,including DVB-S,DVB-S2,and ABS-S.The cut-off frequency of the baseband circuit can be changed continuously from 4.5 to 32 MHz.The gain adjustment range is from 6 to 55.5 dB with 0.5 dB step.The calibration includes automatic frequency tuning（AFT） and automatic DC offset calibration （DCOC） to achieve less than 6%cut-off frequency deviation and 3 mV residual output offset.The out-of-band IIP2 and IIP3 of the overall chain are 45 dBm and 18 dBm respectively,while the input referred noise（IRN） is 17.4 nV/√Hz.All circuit blocks are operated at 2.8 V from LDO and consume current of 20.4 mA in the receiving mode.
基金Supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China(No.2012ZX03004008)
文摘This paper presented an automatic gain control （AGC） circuit suitable for FM/cw ladar. The proposed architecture was based on two-stage variable gain amplifier （VGA） chain with a novel DC offset canceller circuit, which contained an improved Gilbert cell and a Gm-C feedback loop. To keep the VGA with a linearity in dB characteristic, an improved exponential gain control circuit was introduced. The AGC was implemented in 0.18 gm standard CMOS process. Simulation and measurement results verified that its gain ranged from -20 dB to 30 dB, and band- width ranged from 100 kHz to 10 MHz. Its power consumption was 19.8 mW under a voltage supply of 3.3 V.
基金supported by the National Found for Fostering Talents of Basic Science,China(No.J0730318)the National Science and Technology Maior Project,China(Nos.J2009ZX03007-001-03,2010ZX03007-002-03)
文摘This paper designs a binary-weighted programmable gain amplifier（PGA） with a DC offset cancellation （DCOC） circuit and an AB-class output buffer.The PGA adopts the circuit topology of a differential amplifier with diode-connected loads.Simulation shows that the performance of the PGA is not sensitive to temperature and process variation.According to test results,controlled by a digital signal of six bits,the PGA can realize a dynamic gain of-2 to 61 dB,and a gain step of 1 dB with a step error within±0.38 dB.The minimum 3 dB bandwidth is 92 MHz.At low-gain mode,IIP3 is 17 dBm,and a 1 dB compression point can reach 5.7 dBm.The DCOC circuit enables the amplifier to be used in a direct-conversion receiver and the AB-class output buffer circuit reduces the overall static power consumption.
基金Project supported by the National High Technology Research and Development Program of China(No.2011AA010404)the GeneralProgram for International Science and Technology Cooperation Projects of China(No.2010DFB13040)+1 种基金the National Natural Science Foundation of China(No.61076028)the Doctoral Program of Higher Education of China(No.20100071120026)
文摘A high speed inductorless limiting amplifier （LA） in an optical communication receiver with the work- ing speed up to 20 Gb/s is presented. The LA includes an input matching network, a four-stage 3rd order amplifier core, an output buffer for the test and a DC offset cancellation （DCOC）. It uses the active interleaving feedback technique both to broaden the bandwidth and achieve the flatness response. Based on our careful analysis of the DCOC and stability, an error amplifier is added to the DCOC loop in order to keep the offset voltage reasonable. Fabricated in the 65 nm CMOS technology, the LA only occupies an area of 0.45 × 0.25 mm2 （without PAD）. The measurement results show that the LA achieves a differential voltage gain of 37 dB, and a 3-dB bandwidth of 16.5 GHz. Up to 26.5 GHz, the Sddlm and Sdd22 are less than -16 dB and -9 dB. The chip excluding buffer is supplied by 1.2 V VDD and draws a current of 50 mA.
基金Project supported by the Important National Science & Technology Specific Projects,China(No.2010ZX03001-004)the National High Technology Research and Development Program of China(No.2009AA011605)
文摘A design of high dynamic range linear radio frequency power detector （PD）, aimed for transmitter carrier leakage suppression is presented in this paper. Based on the logarithmic amplifier principle, this detector utilizes the successive detection method to achieve a high dynamic range in the radio frequency band. In order to increase sensitivity, a low noise amplifier （LNA） is placed in the front of this detector. DC coupling is adopted in this architecture to reduce parasitics and save area, but this will unavoidably cause DC offsets in the circuit which are detrimental to the dynamic range. So a DC offset cancelling （DCOC） technique is proposed to solve the problem. Finally, this detector was fabricated in the SMIC 0.13μm CMOS process. The measured results show that it achieves a wide dynamic range of 50 dB/40 dB with log errors in 4-1 dB at 900 MHz/2 GHz, while draws 16 mA from a 1.5 V power supply. The active chip area is 0.27×0.67 mm2.
基金Project supported by the National Natural Science Foundation of China(Nos.61106024,61201176)the Specialized Research Fund for the Doctoral Program of Higher Education,China(No.20090092120012)the Special Fund of Jiangsu Province for the Transformation of Scientific and Technological Achievements(No.BA2011009)
文摘An analog baseband circuit of high linearity and high gain accuracy for a digital audio broadcasting receiver is implemented in a 0.18-μm RFCMOS process.The circuit comprises a 3rd-order active-RC complex filter（CF） and a programmable gain amplifier（PGA）.An automatic tuning circuit is also designed to tune the CF＇s pass band.Instead of the class-A fully differential operational amplifier（FDOPA） adopted in the conventional CF and PGA design,a class-AB FDOPA is specially employed in this circuit to achieve a higher linearity and gain accuracy for its large current swing capability with lower static current consumption.In the PGA circuit,a novel DC offset cancellation technique based on the MOS resistor is introduced to reduce the settling time significantly.A reformative switching network is proposed,which can eliminate the switch resistor＇s influence on the gain accuracy of the PGA.The measurement result shows the gain range of the circuit is 10-50 dB with a 1-dB step size,and the gain accuracy is less than ±0.3 dB.The OIP3 is 23.3 dBm at the gain of 10 dB.Simulation results show that the settling time is reduced from 100 to 1 ms.The image band rejection is about 40 dB.It only draws 4.5 mA current from a 1.8 V supply voltage.
文摘An analog baseband circuit for a direct conversion wireless local area network（WLAN） transceiver in a standard 0.13-μm CMOS occupying 1.26 mm^2 is presented.The circuit consists of active-RC receiver（RX） 4th order elliptic lowpass filters（LPFs）,transmitter（TX） 3rd order Chebyshev LPFs,RX programmable gain amplifiers （PGAs） with DC offset cancellation（DCOC） servo loops,and on-chip output buffers.The RX baseband gain can be programmed in the range of -11 to 49 dB in 2 dB steps with 50-30.2 nV/（Hz）^（1/2） input referred noise（IRN） and a 21 to -41 dBm in-band 3rd order interception point（IIP3）.The RX/TX LPF cutoff frequencies can be switched between 5 MHz,10 MHz,and 20 MHz to fulfill the multimode 802.11b/g/n requirements.The TX baseband gain of the I/Q paths are tuned separately from -1.6 to 0.9 dB in 0.1 dB steps to calibrate TX 1/Q gain mismatches.By using an identical integrator based elliptic filter synthesis method together with global compensation applied to the LPF capacitor array,the power consumption of the RX LPF is considerably reduced and the proposed chip draws 26.8 mA/8 mA by the RX/TX baseband paths from a 1.2 V supply.
