A time-domain digitally controlled oscillator composed of a free running ring oscillator and flying-adder

A time-domain digitally controlled oscillator （DCO） is proposed. The DCO is composed of a free-running ring oscillator （FRO） and a two lap-selectors integrated flying-adder （FA）. With a coiled cell array which allows uniform loading capacitances of the delay cells, the FRO produces 32 outputs with consistent tap spacing for the FA as reference clocks. The FA uses the outputs from the FRO to generate the output of the DCO according to the control number, resulting in a linear dependence of the output period, instead of the frequency on the digital controlling word input. Thus the proposed DCO ensures a good conversion linearity in a time-domain, and is suitable for time-domain all-digital phase locked loop applications. The DCO was implemented in a standard 0.13μm digital logic CMOS process. The measurement results show that the DCO has a linear and monotonic tuning curve with gain variation of less than 10%, and a very low root mean square period jitter of 9.3 ps in the output clocks. The DCO works well at supply voltages ranging from 0.6 to 1.2 V, and consumes 4 mW of power with 500 MHz frequency output at 1.2 V supply voltage.

A low-power and low-phase-noise LC digitally controlled oscillator featuring a novel capacitor bank

A monolithic low-power and low-phase-noise digitally controlled oscillator （DCO） based on a symmetric spiral inductor with center-tap and novel capacitor bank was implemented in a 0.18 μm CMOS process with six metal layers. A third new way to change capacitance is proposed and implemented in this work. Results show that the phase noise at I MHz offset frequency is below -122.5 dBc/Hz while drawing a current of only 4.8 mA from a 1.8 V supply. Also, the DCO can work at low supply voltage conditions with a 1.6 V power supply and 4.1 mA supply current for the DCO＇s core circuit, achieving a phase-noise of-121.5 dBc/Hz at offset of 1 MHz. It demonstrates that the supply pushing of DCO is less than 10 MHz/V.

Digitally controlled oscillator design with a variable capacitance XOR gate

A digitally controlled oscillator（DCO） using a three-transistor XOR gate as the variable load has been presented.A delay cell using an inverter and a three-transistor XOR gate as the variable capacitance is also proposed. Three-,five- and seven-stage DCO circuits have been designed using the proposed delay cell.The output frequency is controlled digitally with bits applied to the delay cells.The three-bit DCO shows output frequency and power consumption variation in the range of 3.2486-4.0267 GHz and 0.6121-0.3901 mW,respectively,with a change in the control word 111-000.The five-bit DCO achieves frequency and power of 1.8553-2.3506 GHz and 1.0202-0.6501 mW,respectively,with a change in the control word 11111-00000.Moreover,the seven-bit DCO shows a frequency and power consumption variation of 1.3239-1.6817 GHz and 1.4282-0.9102 mW,respectively, with a varying control word 1111111-0000000.The power consumption and output frequency of the proposed circuits have been compared with earlier reported circuits and the present approaches show significant improvements.

A digitally controlled power amplifier with neutralization capacitors for Zigbee^(TM) applications

This paper presents a single chip CMOS power amplifier with neutralization capacitors for ZigbeeTM system according to IEEE 802.15.4. A novel structure with digital interface is adopted, which allows the output power ofa PA to be controlled by baseband signal directly, so there is no need for DAC. The neutralization capacitors will increase reverse isolation. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed power amplifier has a 13.5 dB power gain, 3.48 dBm output power and 35.1% PAE at P I dB point. The core area is 0.73 × 0.55 mm2.

Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate

Digital controlled oscillators（DCOs） are the core of all digital phase locked loop（ADPLL） circuits. Here,DCO structures with reduced hardware and power consumption having full digital control have been proposed. Three different DCO architectures have been proposed based on ring based topology.Three,four and five bit controlled DCO with NMOS,PMOS and NMOS PMOS transistor switching networks are presented.A three-transistor XNOR gate has been used as the inverter which is used as the delay cell.Delay has been controlled digitally with a switch network of NMOS and PMOS transistors.The three bit DCO with one NMOS network shows frequency variations of 1.6141-1.8790 GHz with power consumption variations 251.9224-276.8591μW. The four bit DCO with one NMOS network shows frequency variation of 1.6229-1.8868 GHz with varying power consumption of 251.9225-278.0740μW.A six bit DCO with one NMOS switching network gave an output frequency of 1.7237-1.8962 GHz with power consumption of 251.928-278.998μW.Output frequency and power consumption results for 4 6 bit DCO circuits with one PMOS and NMOS PMOS switching network have also been presented.The phase noise parameter with an offset frequency of 1 MHz has also been reported for the proposed circuits.Comparisons with earlier reported circuits have been made and the present approach shows advantages over previous circuits.

Control Strategies for Digital Twin Systems

With the continuous breakthrough in information technology and its integration into practical applications, industrial digital twins are expected to accelerate their development in the near future. This paper studies various control strategies for digital twin systems from the viewpoint of practical applications.To make full use of advantages of digital twins for control systems, an architecture of digital twin control systems, adaptive model tracking scheme, performance prediction scheme, performance retention scheme, and fault tolerant control scheme are proposed. Those schemes are detailed to deal with different issues on model tracking, performance prediction, performance retention, and fault tolerant control of digital twin systems. Also, the stability of digital twin control systems is analysed. The proposed schemes for digital twin control systems are illustrated by examples.

Analysis and design of DSP-based dual-loop controlled UPS inverters

This paper presents a novel digital dual-loop control scheme of the PWM(PUlse width modulate)inverter. Deadbeat control technique are employed to enhance the performance. Half switching period delayed sampling and control timing strategy is used to improve the system dynamic response. Simulation and experimental results presented in the paper verified the validity of the proposed control scheme.

Design of low-power high-frequency digital controlled DC-DC switching power converter

This paper models a low-power high-frequency digitally controlled synchronous rectifier （SR） OUCK converter. The converter is a hybrid system with three operation modes. Digital PID controler is used. Key problems such as quantization resolution of digital pulse-width modulation （DPWM） and steady-state limit cycles of digital control switching model power supply （SMPS） are discussed, with corresponding solutions presented. Simulation of a digital control synchronous buck is performed with a fixed-point algorithm. The results show that the described approach enables high-speed dynamic performance.

Study of modeling and simulation of full digital controlled PMIG/MAG welding system based on Matlab/Simulink

This paper presents an integrated simulation model for full digital controlled PMIG/MAG welding system with Matlab/Simulink, and it consists of power inverter, digital control system and dynamic arc-load model. An integrated simulation study was done for full digital PMIG/MAG welding, and a method of connecting dynamic arc-load model to the system with controlled current source was presented, in addition, the simulation results were utilized to study the issues of digital control PMIG/MAG welding in this paper. The experimental results validated the developed simulation model, and this simulation study can be applied in implementation of the full digital PMIG/MAG welding and analysis of system dynamic process.

A digital controlled alternating electromagnetic stirring generator based on dual inverter structure

A digital controlled alternating electromagnetic stirring generator is proposed in this paper. The main circuit of the generator makes use of dual inverter structure among which the former inverter uses full bridge zero voltage switching topology and the latter inverter uses full bridge inverter circuit. To improve the dynamic response performance, the inverting frequency of the former inverter is as high us 100 kHz. The Cortex-M3 kernel based ARM microcontroller LM3S818 is adopted as the cybernetics core of the digital control system to achieve accurate, stable and flexible control of the generator. All the PWM signals for the former and latter inverters are generated by the LM3S818 directly. The constant current characteristic of the former inverter is obtained through current close-loop feedback control, and can ensure the operation safety when the output current waveform is at zero crossing point. Both simulation and experiment results show that the proposed generator is with such advantages as wide soft-switching range, perfect control accuracy and flexible waveform modulation, and can fulfill the requirements of electromagnetic stirring process.

An 80-GHz DCO utilizing improved SC ladder and promoted DCTL-based hybrid tuning banks

An 80-GHz DCO based on modified hybrid tuning banks is introduced in this paper.To achieve sub-MHz frequency res-olution with reduced circuit complexity,the improved circuit topology replaces the conventional circuit topology with two binary-weighted SC cells,enabling eight SC-cell-based improved SC ladders to achieve the same fine-tuning steps as twelve SC-cell-based conventional SC ladders.To achieve lower phase noise and smaller chip size,the promoted binary-weighted digi-tally controlled transmission lines(DCTLs)are used to implement the coarse and medium tuning banks of the DCO.Compared to the conventional thermometer-coded DCTLs,control bits of the proposed DCTLs are reduced from 30 to 8,and the total length is reduced by 34.3%(from 122.76 to 80.66μm).Fabricated in 40-nm CMOS,the DCO demonstrated in this work fea-tures a small fine-tuning step(483 kHz),a high oscillation frequency(79-85 GHz),and a smaller chip size(0.017 mm^(2)).Com-pared to previous work,the modified DCO exhibits an excellent figure of merit with an area(FoMA)of-198 dBc/Hz.

Applicahon of a Simplified Model Reference Adaptive Algorithm

The application of a simplifed model reference adaptive control(SMRAC) on a typical Pump controlled motor electrohydraulic servo system is studied here. The algorithm of first-order scalar SMRAC ac second-order vector SMRAC are derived. Computer simulations of the algorithms are presented. Experimental results prove that the method of control adopted here perform satisfactorily over a wide range of operating conditions.

Threshold decision for instrument control system and its application in nuclear power plant

Threshold decision is an important function of nuclear instrument control system based on physical parameters threshold decision. Because the conventional decision methods lack correlation with time and conditions, by analyzing the existing methods, some optimized methods are adopted. Considering safety, those methods are improved in data processing algorithms, floating threshold with multiple values, association with specific working condition, etc. These measures im- prove the nuclear instrument control system in fault tolerance and fault diagnosis, especially, the shutdown number of nucle- ar power plant decreases.

2D DIGITAL SIMPLIFIED FLOW VALVE

The 2D digital simplified flow valve is composed of a pilot-operated valvedesigned with both rotary and linear motions of a single spool, and a stepper motor under continualcontrol. How the structural parameters affect the static and dynamic characteristics of the valve isfirst clarified and a criterion for stability is presented. Experiments are designed to test theperformance of the valve. It is necessary to establish a balance between the static and dynamiccharacteristics in deciding the structural parameters. Nevertheless, it is possible to maintain thedynamic response at a fairly high level, while keeping the leakage of the pilot stage at anacceptable level. One of the features of the digital valve is stage control. In stage control thenonlinearities, such as electromagnetic saturation and hysteresis, are greatly reduced. To a largeextent the dynamic response of the valve is decided by the executing cycle of the control algorithm.

Iterative Learning Control for Discrete-time Stochastic Systems with Quantized Information

An iterative learning control (ILC) algorithm using quantized error information is given in this paper for both linear and nonlinear discrete-time systems with stochastic noises. A logarithmic quantizer is used to guarantee an adaptive improvement in tracking performance. A decreasing learning gain is introduced into the algorithm to suppress the effects of stochastic noises and quantization errors. The input sequence is proved to converge strictly to the optimal input under the given index. Illustrative simulations are given to verify the theoretical analysis. © 2014 Chinese Association of Automation.

Digital Servo Control of a Robotic Excavator

An electro-hydraulic control system is designed and implemented for a robotic excavator known as the Lancaster University Computerised and Intelligent Excavator （LUCIE）. The excavator is being developed to autonomously dig trenches without human intervention. Since the behavior of the excavator arm is dominated by the nonlinear dynamics of the hydraulic actuators and by the large and unpredictable external disturbances when digging, it is difficult to provide adequate accurate, quick and smooth movement under traditional control methodology, e.g., PI/PID, which is comparable with that of an average human operator. The data-based dynamic models are developed utilizing the simplified refined instrumental variable （SRIV） identification algorithm to precisely describe the nonlinear dynamical behaviour of the electro-hydraulic actuation system. Based on data-based model and proportional-integral-plus （PIP） methodology, which is a non-minimal state space method of control system design based on the true digital control （TDC） system design philosophy, a novel control system is introduced to drive the excavator arm accurately, quickly and smoothly along the desired path. The performance of simulation and field tests which drive the bucket along straight lines both demonstrate the feasibility and validity of the proposed control scheme.

Design of speed controller for electronic fuel injection gasoline generator based on feed-forward PID control

As for the application of electronic fuel injection （EFI） system to small gasoline generator set, mechanical speed controller cannot be coupled with EFI system and has the shortcomings of lagged regulation and poor accuracy, a feed-forward control strategy based on load combined with proportional-integral-differential （PID） control strategy was proposed, and a digital speed controller applied to the electrical control system was designed. The detailed control strategy of the controller was intro- duced. The hardware design for the controller and the key circuits of motor driving, current sampling and angular signal captu- ring were given, and software architecture was discussed. Combined with a gasoline generator set mounted with EFI system, the controller parameters were tuned and optimized empirically by hardware in loop and bench test methods. Test results show that the speed deviation of generator set is low and the control system is stable in steady state; In transient state the control system responses quickly, has high stability under mutation loads especially when suddenly apply and remove 100% load, the speed deviation is within 8% of reference speed and the transient time is less than 5 s, satisfying the ISO standard.

Design and Implementation of Digital Fractional Order PID Controller Using Optimal Pole-Zero Approximation Method for Magnetic Levitation System

The aim of this paper is to employ fractional order proportional integral derivative(FO-PID)controller and integer order PID controller to control the position of the levitated object in a magnetic levitation system(MLS),which is inherently nonlinear and unstable system.The proposal is to deploy discrete optimal pole-zero approximation method for realization of digital fractional order controller.An approach of phase shaping by slope cancellation of asymptotic phase plots for zeros and poles within given bandwidth is explored.The controller parameters are tuned using dynamic particle swarm optimization(d PSO)technique.Effectiveness of the proposed control scheme is verified by simulation and experimental results.The performance of realized digital FO-PID controller has been compared with that of the integer order PID controllers.It is observed that effort required in fractional order control is smaller as compared with its integer counterpart for obtaining the same system performance.

Next-generation power delivery system with resiliency and environmental affinity

Renewable energy resources play an important role in the realization of the carbon neutrality.The microgrid can efficiently integrate numerous renewable energy systems into power distribution systems to realize power supply resiliency and environmental affinity.This paper reviews the current trend of microgrid and networked microgrid technologies worldwide,particularly in Japan,including the Flexible,Reliable,and Intelligent Energy Delivery System(FRIENDS)and some other examples of the networked microgrid.Some recent digitalized control functions of the microgrid and related systems are also introduced.

A comparative study of digital low dropout regulators

Granular power management in a power-efficient system on a chip(SoC)requires multiple integrated voltage regulators with a small area,process scalability,and low supply voltage.Conventional on-chip analog low-dropout regulators(ALDOs)can hardly meet these requirements,while digital LDOs(DLDOs)are good alternatives.However,the conventional DLDO,with synchronous control,has inherently slow transient response limited by the power-speed trade-off.Meanwhile,it has a poor power supply rejection(PSR),because the fully turned-on power switches in DLDO are vulnerable to power supply ripples.In this comparative study on DLDOs,first,we compare the pros and cons between ALDO and DLDO in general.Then,we summarize the recent DLDO advanced techniques for fast transient response and PSR enhancement.Finally,we discuss the design trends and possible directions of DLDO.