Generation of Optimal Voltage Reference for Limit Cycle Oscillation in Digital Control-Based Switching Power Supply

Digital control of a general-purpose switching power supply is one of the key technologies to perform the high reliability and the intelligent function demanded for the next generation. The contribution of this paper is the development of a digital control-based switching power supply. In the developed system, the generation method of the optimal voltage reference to eliminate the limit cycle oscillation of output voltage due to the AD/DA resolution is proposed. In the proposed method, the variation of the input power source voltage can be also compensated. The effectiveness of the proposed optimal reference generation method is experimentally verified.

Digitally controlled oscillator design with a variable capacitance XOR gate

A digitally controlled oscillator（DCO） using a three-transistor XOR gate as the variable load has been presented.A delay cell using an inverter and a three-transistor XOR gate as the variable capacitance is also proposed. Three-,five- and seven-stage DCO circuits have been designed using the proposed delay cell.The output frequency is controlled digitally with bits applied to the delay cells.The three-bit DCO shows output frequency and power consumption variation in the range of 3.2486-4.0267 GHz and 0.6121-0.3901 mW,respectively,with a change in the control word 111-000.The five-bit DCO achieves frequency and power of 1.8553-2.3506 GHz and 1.0202-0.6501 mW,respectively,with a change in the control word 11111-00000.Moreover,the seven-bit DCO shows a frequency and power consumption variation of 1.3239-1.6817 GHz and 1.4282-0.9102 mW,respectively, with a varying control word 1111111-0000000.The power consumption and output frequency of the proposed circuits have been compared with earlier reported circuits and the present approaches show significant improvements.

A low-power and low-phase-noise LC digitally controlled oscillator featuring a novel capacitor bank

A monolithic low-power and low-phase-noise digitally controlled oscillator （DCO） based on a symmetric spiral inductor with center-tap and novel capacitor bank was implemented in a 0.18 μm CMOS process with six metal layers. A third new way to change capacitance is proposed and implemented in this work. Results show that the phase noise at I MHz offset frequency is below -122.5 dBc/Hz while drawing a current of only 4.8 mA from a 1.8 V supply. Also, the DCO can work at low supply voltage conditions with a 1.6 V power supply and 4.1 mA supply current for the DCO＇s core circuit, achieving a phase-noise of-121.5 dBc/Hz at offset of 1 MHz. It demonstrates that the supply pushing of DCO is less than 10 MHz/V.

A time-domain digitally controlled oscillator composed of a free running ring oscillator and flying-adder

A time-domain digitally controlled oscillator （DCO） is proposed. The DCO is composed of a free-running ring oscillator （FRO） and a two lap-selectors integrated flying-adder （FA）. With a coiled cell array which allows uniform loading capacitances of the delay cells, the FRO produces 32 outputs with consistent tap spacing for the FA as reference clocks. The FA uses the outputs from the FRO to generate the output of the DCO according to the control number, resulting in a linear dependence of the output period, instead of the frequency on the digital controlling word input. Thus the proposed DCO ensures a good conversion linearity in a time-domain, and is suitable for time-domain all-digital phase locked loop applications. The DCO was implemented in a standard 0.13μm digital logic CMOS process. The measurement results show that the DCO has a linear and monotonic tuning curve with gain variation of less than 10%, and a very low root mean square period jitter of 9.3 ps in the output clocks. The DCO works well at supply voltages ranging from 0.6 to 1.2 V, and consumes 4 mW of power with 500 MHz frequency output at 1.2 V supply voltage.

Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate

Digital controlled oscillators（DCOs） are the core of all digital phase locked loop（ADPLL） circuits. Here,DCO structures with reduced hardware and power consumption having full digital control have been proposed. Three different DCO architectures have been proposed based on ring based topology.Three,four and five bit controlled DCO with NMOS,PMOS and NMOS PMOS transistor switching networks are presented.A three-transistor XNOR gate has been used as the inverter which is used as the delay cell.Delay has been controlled digitally with a switch network of NMOS and PMOS transistors.The three bit DCO with one NMOS network shows frequency variations of 1.6141-1.8790 GHz with power consumption variations 251.9224-276.8591μW. The four bit DCO with one NMOS network shows frequency variation of 1.6229-1.8868 GHz with varying power consumption of 251.9225-278.0740μW.A six bit DCO with one NMOS switching network gave an output frequency of 1.7237-1.8962 GHz with power consumption of 251.928-278.998μW.Output frequency and power consumption results for 4 6 bit DCO circuits with one PMOS and NMOS PMOS switching network have also been presented.The phase noise parameter with an offset frequency of 1 MHz has also been reported for the proposed circuits.Comparisons with earlier reported circuits have been made and the present approach shows advantages over previous circuits.

一种基于DCO的可配置数字频率合成器

首先设计了一种基于MDLL的数控振荡器(DCO),进而实现了一种基于DCO的全数字可配置的数字频率合成器(DFS),输出时钟频率等于参考时钟频率乘以M除以D,实现了类似于MDLL的抖动特性.频率合成器提供一个可配置的倍频因子M和一个分频因子D,其范围为2~32和1~32,用户可以通过对M和D的配置,实现任意倍数的频率合成.所设计的DFS采用TSMC的0.13mm标准CMOS工艺实现,版图面积为480μm×120μm.DFS的输出频率范围为15~400 MHz,输入频率范围为1~270 MHz.输出频率为270 MHz时实测的相位噪声为-110.01dBc/Hz@1 MHz.

THE DESIGN OF AN ALL-DIGITAL PHASE-LOCKED LOOP WITH LOW JITTER BASED ON ISF ANALYSIS

A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.

An 80-GHz DCO utilizing improved SC ladder and promoted DCTL-based hybrid tuning banks

An 80-GHz DCO based on modified hybrid tuning banks is introduced in this paper.To achieve sub-MHz frequency res-olution with reduced circuit complexity,the improved circuit topology replaces the conventional circuit topology with two binary-weighted SC cells,enabling eight SC-cell-based improved SC ladders to achieve the same fine-tuning steps as twelve SC-cell-based conventional SC ladders.To achieve lower phase noise and smaller chip size,the promoted binary-weighted digi-tally controlled transmission lines(DCTLs)are used to implement the coarse and medium tuning banks of the DCO.Compared to the conventional thermometer-coded DCTLs,control bits of the proposed DCTLs are reduced from 30 to 8,and the total length is reduced by 34.3%(from 122.76 to 80.66μm).Fabricated in 40-nm CMOS,the DCO demonstrated in this work fea-tures a small fine-tuning step(483 kHz),a high oscillation frequency(79-85 GHz),and a smaller chip size(0.017 mm^(2)).Com-pared to previous work,the modified DCO exhibits an excellent figure of merit with an area(FoMA)of-198 dBc/Hz.

计及数字控制延时影响的含PMSG电力系统的宽频振荡z域阻抗判据研究

随着大量数字控制被应用于永磁直驱风电机组,受数字控制延时影响,含永磁直驱风电机组电力系统的宽频振荡问题日益突出。为了深入分析宽频振荡失稳机理以及快速准确地评估系统稳定性,提出了一种新的阻抗建模方法和稳定性判据。首先,基于精确离散化方法将含有延时环节的永磁直驱风电机组以及受端交流电网中的系统元件分别建模成锁相环坐标系下的z域阻抗模型。根据电路原理,将所有系统元件聚合成z域聚合阻抗模型,以此作为后续理论发展的模型基础。然后,基于盖尔圆定理,提出广义禁区判据来分析系统稳定性。最后,在Matlab/Simulink中搭建含永磁直驱风电机组的改进IEEE 3机9节点模型验证所提方法的有效性。

一种高性能的全数字锁相环设计方案

针对实现参考频率和输出的频率近似相等或者近似成整数倍关系时遇到的锁相环设计方案复杂以及高性能的模拟锁相环不适宜于集成化问题,设计了主要由模数转换器、全数字式鉴相器、数字式低通滤波器和数控振荡器等构成的全数字式锁相环。主要利用模数转换器在动态量采集时具有的边沿效应从其采集的大量数据中选择出精度更高的数据用于后级的全数字式鉴相,实现了一种全数字式锁相环。实验结果表明了该方案的正确性及其具有锁定精度高和环路的本底噪声低等特性。

基于噪声分析的低抖动全数字锁相环的设计

设计了一个用于时钟产生的全数字锁相环（ADPLL），其数控振荡器（DCO）采用9级环形振荡器，每级延迟单元的延迟时间均是可调的，各级倒相器的尺寸经过精确设计。该电路基于SMIC0．13μm CMOS工艺，采用1．2V电源供电，整个芯片的面积为0．13485mm^2。示波器测试结果表明，锁相环的捕获频率范围为100-500MHz，输出频率为202．75MHz时，峰一峰值抖动为133ps，RMS抖动为46ps。

低频振荡时的汽轮机调速控制方式在线调整策略

现场运行证明,若汽轮发电机组发生低频振荡,则可尝试改变调速系统控制方式以抑制振荡。已有研究表明,若电网侧的低频电功率振荡扰动引起机械功率共振,会使转子角振幅大幅增加。因此,分析了汽轮发电机组调速系统在串级比例—积分(PI)和2种单级PI控制方式下的阻尼特性和频率特性,提出了控制方式的调整策略,以避开共振频率点。仿真表明,发生共振时,通过调整调速系统的控制方式,能有效地降低转子振幅。该方法依托调速系统的现有功能进行低频振荡抑制,便捷有效且能在线调整,对系统的稳定运行具有现实意义。

并行数字下变频中的NCO实现研究

受数字信号处理器件处理速度的制约,宽带数字中频处理带宽、滤波器性能等重要指标难以提高。硬件实现时FPGA(field programmable gate array)无法提供与采样率相匹配的数据处理速度直接对原始采样数据下变频,将多相结构应用到传统的数字下变频运算中。推导了应用于数字下变频多相结构的多路NCO(numerically controlled oscillator)数字本振信号数学表达式,并讨论了在FPGA中实现多路NCO时相关参数的选取原则。MATLAB仿真结果及硬件平台验证了采用多路NCO本振信号实现数字下变频的正确性。

增益恒定的数控振荡器设计

针对驱动能力可调的数控振荡器在输出频率范围内增益变化较大的问题,提出了一种电路设计方法,通过该方法设计出的数控振荡器结构具有增益恒定的特点。在SMIC 0.18μm logic 1P6M CMOS工艺下设计并实现了一个采用该振荡器结构的数控锁相环,数控振荡器的面积为0.025 mm2。实测数据表明,该数控振荡器输出的频率范围为76～208 MHz。当锁相环输出208 MHz高频时钟时,四分频后的峰峰值抖动为110 ps,均方根抖动为14.82 ps,数控振荡器的功耗为1.512 mW。

一种快速锁定数控锁相环

提出了一种快速锁定数控锁相环结构.该锁相环具有频率捕获模式和相位捕获模式2种工作模式.在频率捕获模式,通过提出的一种新的算法,可以迅速缩小参考时钟和反馈时钟之间的频率差.在相位捕获模式,数控锁相环能够达到更精确的相位锁定.为了验证提出的数控锁相环结构和算法,该数控锁相环电路采用SMIC0.18μm logic1P6M CMOS工艺实现,面积为0.2mm^2,频率范围为48-416MHz.实测结果表明,数控锁相环只需要2个参考时钟周期就锁定在376MHz.数控锁相环锁定后功耗为11.394mW,峰峰值抖动为92ps,周期抖动为14.49ps.

基于TDC的GPS驯服恒温晶振系统设计

为满足测控系统对高精度时间频率的要求,设计了一种基于时间数字转换器(TDC)的驯服恒温晶振系统。使用GPS对恒温晶振进行实时校准,获得了高精度的频率信号。通过TDC测量时差数据计算得到恒温晶振的频率准确度,其时差测量精度达到250 ps。采用优化的递推平均滤波算法对时差数据进行滤波处理,消除了GPS秒信号抖动引入的干扰,缩短了频率驯服时间,频率驯服精度优于3×10-11。

新型 CMOS 数控振荡器

提出了一种新型ＣＭＯＳ数控振荡器的设计．该振荡器由一个结构简单的电流控制振荡器和一组可数控的电流源电路构成，电路结构简单，非常适合作为ＡＳＩＣ单元电路使用，既可单独作为数控振荡器使用，也可用作为数字锁相环中的一个部件．计算机电路模拟结果表明，新型ＣＭＯＳ数控振荡器具有较高的自激振荡频率、较宽的频率变化范围及较高的频率控制精度等特性，在计算机接口电路中有着良好的应用前景．

数控高频振荡器的设计

介绍了目前常用的数控延迟单元电路结构,详细分析了这些电路的优缺点。在此基础上,对其中一种电路结构进行了详细的理论分析,改进了电路结构,规范了电路设计的具体步骤,并通过大量的电路模拟,印证了理论分析的正确性。以此延迟单元为核心,在SMIC 0.13μm工艺下,设计实现了一款数控高频振荡器。该振荡器的频率范围高达700 MHz,最高稳定输出频率可达到1 GHz。由于采用全数字实现方式,其功耗最大值不到0.7 mW,版图面积只有26μm×36μm。该电路已成功应用于一个锁相环电路的设计中。

硅微机械陀螺自激驱动数字化技术

为了进一步增强硅微机械陀螺仪驱动模态的控制精度与稳定性,提出了一种基于自激振荡原理,以现场可编程门阵列(FPGA)为主要数字信号处理平台的驱动电路。以陀螺仪驱动模态特性为出发点,分析了自激振荡原理对驱动电路的要求。分析并建立了驱动相位控制与驱动幅度控制模型,实现了频率测量-补偿算法控制驱动环路相位,PID控制算法控制环路幅度。实验结果表明,常温下驱动幅度控制精度达到1.5×10-5,并且能跟踪驱动模态谐振频率。由于采用了数字电路使得驱动幅度温度系数由原来模拟电路方案的7.69×10-5/℃降低到1.183×10-5/℃。相比传统模拟电路控制方案,本方案具有驱动精度高,温度适应性好的优点。

恒定导通时间控制Buck变换器的间隔周期斜率补偿方案

提出一种改进的斜率补偿方式,用以改善恒定导通时间控制模式Buck变换器的稳定性。与传统方法相比,所提方法以数字化控制的方式间隔周期提供斜率补偿信号,能更加有效地消除次谐波振荡。此外,该方法可根据相邻周期关断时间的偏差来自适应地调节补偿信号的斜率。这使得系统在稳态时仅需少量的斜率补偿,有效地降低了补偿信号对恒定导通时间控制快速响应能力的影响。通过理论量化分析和实验对比验证了所提方法的可行性。