The Viral Load of Epstein-Barr Virus in Blood of Children after Hematopoietic Stem Cell Transplantation

Objective To detect the Epstein-Barr virus(EBV)viral load of children after hematopoietic stem cell transplantation(HSCT)using chip digital PCR(cdPCR).Methods The sensitivity of cdPCR was determined using EBV plasmids and the EBV B95-8 strain.The specificity of EBV cdPCR was evaluated using the EBV B95-8 strain and other herpesviruses(herpes simplex virus 1,herpes simplex virus 2,varicella zoster virus,human cytomegalovirus,human herpesvirus 6,and human herpesvirus 7).From May 2019 to September 2020,64 serum samples of children following HSCT were collected.EBV infection and the viral load of serum samples were detected by cdPCR.The epidemiological characteristics of EBV infections were analyzed in HSCT patients.Results The limit of detection of EBV cdPCR was 110 copies/mL,and the limit of detection of EBV quantitative PCR was 327 copies/mL for the pUC57-BALF5 plasmid.The result of EBV cdPCR was up to 121 copies/mL in the EBV B95-8 strain,and both were more sensitive than that of quantitative PCR.Using cdPCR,the incidence of EBV infection was 18.75%in 64 children after HSCT.The minimum EBV viral load was 140 copies/mL,and the maximum viral load was 3,209 copies/mL using cdPCR.The average hospital stay of children with EBV infection(184±91 days)was longer than that of children without EBV infection(125±79 days),P=0.026.Conclusion EBV cdPCR had good sensitivity and specificity.The incidence of EBV infection was 18.75%in 64 children after HSCT from May 2019 to September 2020.EBV cdPCR could therefore be a novel method to detect EBV viral load in children after HSCT.

A Low Power Non-Volatile LR-WPAN Baseband Processor with Wake-Up Identification Receiver

The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.

An introduction and review on innovative silicon implementations of implantable/scalp EEG chips for data acquisition, seizure/behavior detection, and brain stimulation

Technological advances in the semiconductor industry and the increasing demand and development of wearable medical systems have enabled the development of dedicated chips for complex electroencephalogram(EEG)signal processing with smart functions and artificial intelligence-based detections/classifications.Around 10 million transistors are integrated into a 1 mm2 silicon wafer surface in the dedicated chip,making wearable EEG systems a powerful dedicated processor instead of a wireless raw data transceiver.The reduction of amplifiers and analog-digital converters on the silicon surface makes it possible to place the analog front-end circuits within a tiny packaged chip;therefore,enabling high-count EEG acquisition channels.This article introduces and reviews the state-of-the-art dedicated chip designs for EEG processing,particularly for wearable systems.Furthermore,the analog circuits and digital platforms are included,and the technical details of circuit topology and logic architecture are presented in detail.

CMOS vision sensor with fully digital image process integrated into low power 1/8-inch chip

A digital still camera image processing system on a chip, different from the video camera system, is pre- sented for mobile phone to reduce the power consumption and size. A new color interpolation algorithm is proposed to enhance the image quality. The system can also process fixed patten noise （FPN） reduction, color correction, gamma correction, RGB/YUV space transfer, etc. The chip is controlled by sensor regis- ters by inter-integrated circuit （I2C） interface. The voltage for both the front-end analog and the pad cir- cuits is 2.8 V, and the volatge for the image signal processing is 1.8 V. The chip running under the external 13.5-MHz clock has a video data rate of 30 frames/s and the measured power dissipation is about 75 roW.